AD7305(RevA) Просмотр технического описания (PDF) - Analog Devices
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AD7305 Datasheet PDF : 14 Pages
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AD7304/AD7305
Table III. AD7305 Control Logic Truth Table
WR A1 A0 LDAC Input Register Function
DAC Register Function
LLLH
↑+ L L H
L L HH
↑+ L H H
L HL H
↑+ H L H
L HHH
↑+ H H H
HXXL
L XXL
H X X ↑+
HXXH
REG A Loaded with DB0–DB7
REG A Latched with DB0–DB7
REG B Loaded with DB0–DB7
REG B Latched with DB0–DB7
REG C Loaded with DB0–DB7
REG C Latched with DB0–DB7
REG D Loaded with DB0–DB7
REG D Latched with DB0–DB7
No Effect
Input REG x Transparent to DB0–DB7
No Effect
No Effect, Device Not Selected
Latched with Previous Contents, No Change
Latched with Previous Contents, No Change
Latched with Previous Contents, No Change
Latched with Previous Contents, No Change
Latched with Previous Contents, No Change
Latched with Previous Contents, No Change
Latched with Previous Contents, No Change
Latched with Previous Contents, No Change
All Input Register Contents Loaded, Register Transparent
Register Transparent
All Input Register Contents Latched
No Effect, Device Not Selected
NOTES
1↑+ positive logic transition; ↓– negative logic transition; X Don’t Care.
2LDAC is a level sensitive input.
PIN CONFIGURATIONS
WR
A0, A1
D0–D7
LDAC
VOUT
tWR
tAS
tAH
tDS
tDH
tLS
tLH
tS
tLDW
؎1 LSB
ERROR BAND
Figure 4. AD7305 Timing Diagram
A0/SHDN
tSDN
tSDR
IDD
Figure 5. AD7305 Timing Diagram
VOUTB 1
16 VOUTC
VOUTA 2
15 VOUTD
VSS 3
14 VDD
VREFA 4 AD7304 13 VREFC
VREFB
5
TOP VIEW
(Not to Scale) 12
VREFD
GND 6
11 SDI/SHDN
LDAC 7
10 CLK
CLR 8
9 CS
VOUTB 1
20 VOUTC
VOUTA 2
19 VOUTD
VSS 3
18 VDD
VREF 4
17 A0/SHDN
GND
LDAC
DB7
5 AD7305 16 A1
6
TOP VIEW 15
(Not to Scale)
WR
7
14 DB0
DB6 8
13 DB1
DB5 9
12 DB2
DB4 10
11 DB3
REV. A
–5–
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