AD7305(RevA) Просмотр технического описания (PDF) - Analog Devices

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AD7305
(Rev.:RevA)

+3 V/+5 V, Rail-to-Rail Quad, 8-Bit DAC

Analog Devices 

AD7304/AD7305

CIRCUIT OPERATION

The AD7304/AD7305 are a set of four-channel, 8-bit, voltage-

output, digital-to-analog converters differing primarily in digital

logic interface and number of reference inputs. Both parts share

the same internal DAC design and true rail-to-rail output buff-

ers. The AD7304 contains four independent multiplying refer-

ence inputs, while the AD7305 has one common reference input.

The AD7304 uses a 3-wire SPI compatible serial data interface,

while the AD7305 offers a 8-bit parallel data interface.

D/A Converter Section

Each part contains four voltage-switched R-2R ladder DACs.

Figure A shows a typical equivalent DAC. These DACs are

designed to operate both single-supply or dual supply, depend-

ing on whether the user supplies a negative voltage on the VSS

pin. In a single-supply application the VSS is tied to ground. In

either mode the DAC output voltage is determined by the VREF

input voltage and the digital data (D) loaded into the corre-

sponding DAC register according to Equation 1.

VOUT = VREF × D/256

(1)

Note that the output full-scale polarity is the same as the VREF

polarity for dc reference voltages.

VREF

VDD

DB7 2R

DB6 2R

R VSS

VOUT

DB0 2R

2R

Figure 29. Typical Equivalent DAC Channel

These DACs are also designed to accommodate ac reference

input signals. As long as the ac signals are maintained between

VSS < VREF <VDD, the user can expect 50 kHz of full-power

multiplying bandwidth performance. In order to use negative

input reference voltages, the VSS pin must be biased with a nega-

tive voltage of equal or greater magnitude than the reference

voltage.

The reference inputs are code-dependent, exhibiting worst case

minimum resistance values specified in the parametric specifica-

tion table. The DAC outputs VOUTA, B, C, D are each capable

of driving 2 kΩ loads in parallel with up to 500 pF loads. Output

source and sink current is shown in Figures 6 and 7. The output

slew rate is nominally 3.6 V/µs while operating from ± 5 V sup-

plies. The low output impedance of the buffers minimizes

crosstalk between analog input channels. At 100 kHz, 65 dB of

channel-to-channel isolation exists (Figure 22). Output voltage

noise is plotted in Figure 19. In order to maintain good analog

performance, power supply bypassing of 0.01 µF in parallel with

1 µF is recommended. The true rail-to-rail capability of the

AD7304/AD7305 allows the user to connect the reference inputs

directly to the same supply as the VDD or VSS pin (Figure 30).

Under these conditions clean power supply voltages (low ripple,

avoid switching supplies) appropriate for the application should

be used.

VDD

Q1

VOUTX

120k⍀

Q2

VSS

Figure 30. Equivalent DAC Amplifier Output Circuit

AD7304 SERIAL DATA INTERFACE

The AD7304 uses a 3-wire (CS, SDI, CLK) SPI compatible

serial data interface. New serial data is clocked into the serial

input register in a 12-bit data-word format. MSB bits are loaded

first. Table II defines the 12 data-word bits. Data is placed on

the SDI/SHDN pin and clocked into the register on the positive

clock edge of CLK subject to the data setup and data hold time

requirements specified in the TIMING SPECIFICATIONS.

Data can only be clocked in while the CS chip select pin is

active low. Only the last 12-bits clocked into the serial register

will be interrogated when the CS pin returns to the logic high

state, extra data bits are ignored. Since most microcontrollers

output serial data in 8-bit bytes, two right justified data bytes

can be written to the AD7304. Keeping the CS line low between

the first and second byte transfer will result in a successful serial

register update.

Once the data is properly aligned in the shift register the positive

edge of the CS initiates either the transfer of new data to the

target DAC register, determined by the decoding of address bits

A1 and A0, or the shutdown features will be activated based on

the SAC or SDC bits. When either SAC or SDC pins are set

(Logic = 0) the loading of new data determined by Bits B9 to

B0 are still loaded, but the results do not appear on the buffer

outputs until the device is brought out of the shutdown state.

The selected DAC output voltages become high impedance with

a nominal resistance of 120 kΩ to ground, Figure 30. If both

SAC and SDC pins are set, all channels are still placed in the

shutdown mode. When the AD7304 has been programmed into

the power shutdown state, the present DAC register data is

maintained as long as VDD remains greater than 2.7 volts. The

remaining characteristics of the software serial interface are

defined by Tables I, II and Figure 3 timing diagram.

Two additional pins CLR and LDAC on the AD7304 provide

hardware control over the clear function and the DAC Register

loading. If these functions are not needed the CLR pin can be

tied to logic high, and the LDAC pin can be tied to logic low.

The asynchronous input CLR pin forces all input and DAC

registers to the zero-code state. The asynchronous LDAC pin

can be strobed to active low when all DAC Registers need to be

updated simultaneously from their respective Input Registers.

The LDAC pin places the DAC Register in a transparent mode

while in the logic low state.

REV. A

–11–

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