DS21348 Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated

Номер в каталоге

Компоненты Описание

производитель

DS21348

3.3V E1/T1/J1 Line Interface

Dallas Semiconductor -> Maxim Integrated 

DS21348/Q348

PIN DESCRIPTIONS IN PARALLEL PORT MODE (Sorted by Pin Name,

DS21348T Pin Numbering) Table 4-2b

ACRONYM PIN I/O DESCRIPTION

A0 to A4

11

to

7

ALE(AS)

4

BIS0/BIS1

BPCLK

32/33

31

CS*

1

D0 / AD0

19

to

to

D7 / AD7

12

HRST*

29

INT*

23

MCLK

30

NA

-

PBEO

24

PBTS

44

I Address Bus. In nonmultiplexed bus operation (BIS1 = 0, BIS0 =

1), serves as the address bus. In multiplexed bus operation (BIS1 =

0, BIS0 = 0), these pins are not used and should be tied low.

I Address Latch Enable (Address Strobe). When using the parallel

port (BIS1 = 0) in multiplexed bus mode (BIS0 = 0), serves to

demultiplex the bus on a positive-going edge. In nonmultiplexed bus

mode (BIS0 = 1), should be tied low.

I Bus Interface Select Bits 0 & 1. Used to select bus interface option.

See Table 4-1 for details.

O Back Plane Clock. A 16.384MHz, 8.192MHz, 4.096MHz, or

2.048MHz clock output that is referenced to RCLK selectable via

CCR5.7 and CCR5.6. In hardware mode, defaults to 16.384MHz

output.

I Chip Select. Must be low to read or write to the device. CS* is an

active low signal.

I/O Data Bus/Address/Data Bus. In nonmultiplexed bus operation

(BIS1 = 0, BIS0 = 1), serves as the data bus. In multiplexed bus

operation (BIS1 = 0, BIS0 = 0), serves as an 8-bit multiplexed

address/data bus.

I Hardware Reset. Bringing HRST* low will reset the DS21348

setting all control bits to their default state of all zeros.

O Interrupt [INT*] Pin 23. Flags host controller during conditions

and change of conditions defined in the Status Register. Active low,

open drain output.

I Master Clock. A 2.048MHz (±50ppm) clock source with TTL

levels is applied at this pin. This clock is used internally for both

clock/data recovery and for jitter attenuation. Use of a T1 1.544

MHz clock source is optional.

See Note 2.

I Not Assigned. Should be tied low.

O PRBS Bit Error Output. The receiver will constantly search for a

215-1 or a 220-1 PRBS depending on the ETS bit setting (CCR1.7).

Remains high if out of synchronization with the PRBS pattern. Goes

low when synchronized to the PRBS pattern. Any errors in the

received pattern after synchronization will cause a positive going

pulse (with same period as E1 or T1 clock) synchronous with

RCLK. PRBS bit errors can also be reported to the ECR1 and ECR2

registers by setting CCR6.2 to a logic 1.

I Parallel Bus Type Select. When using the parallel port (BIS1 = 0),

set high to select Motorola bus timing, set low to select Intel bus

timing. This pin controls the function of the RD*(DS*), ALE(AS),

and WR*(R/W*) pins. If PBTS = 1 and BIS1 = 0, then these pins

assume the Motorola function listed in parenthesis (). In serial port

mode, this pin should be tied low.

11 of 73

Share Link: