DS21348 Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated

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производитель

DS21348

3.3V E1/T1/J1 Line Interface

Dallas Semiconductor -> Maxim Integrated 

DS21348T

DS21348G

I/O

Serial

PIN #

PIN#

Port Mode

40

B3

O

RCLK

41

A3

I

TPOS

42

B2

I

TNEG

43

A2

I

TCLK

44

A1

I

NA

DS21348/Q348

PIN DESCRIPTIONS IN SERIAL PORT MODE (Sorted by Pin Name, DS21348T

Pin Numbering) Table 4-3b

ACRONYM PIN I/O DESCRIPTION

BIS0/

32/

I Bus Interface Select Bits 0 & 1. Used to select bus interface option.

BIS1

33

See Table 4-1 for details.

BPCLK

31

O Back Plane Clock. A 16.384MHz, 8.192MHz, 4.096MHz, or

2.048MHz clock output that is referenced to RCLK selectable via

CCR5.7 and CCR5.6. In hardware mode, defaults to 16.384 MHz

output.

CS*

1

I Chip Select. Must be low to read or write to the device. CS* is an

active low signal.

HRST*

29

I Hardware Reset. Bringing HRST* low will reset the DS21348

setting all control bits to their default state of all zeros.

ICES

8

I Input Clock Edge Select. Selects whether the serial port data input

(SDI) is sampled on rising (ICES =0) or falling edge (ICES = 1) of

SCLK.

INT*

23

O Interrupt [INT*] Pin 23. Flags host controller during conditions

and change of conditions defined in the Status Register. Active low,

open drain output.

MCLK

30

I Master Clock. A 2.048MHz (±50ppm) clock source with TTL

levels is applied at this pin. This clock is used internally for both

clock/data recovery and for jitter attenuation. Use of a T1 1.544

MHz clock source is optional.

See Note 2.

NA

-

I Not Assigned. Should be tied low.

OCES

9

I Output Clock Edge Select. Selects whether the serial port data

output (SDO) is valid on the rising (OCES = 1) or falling edge

(OCES = 0) of SCLK.

PBEO

24

O PRBS Bit Error Output. The receiver will constantly search for a

215-1 or a 220-1 PRBS depending on the ETS bit setting (CCR1.7).

Remains high if out of synchronization with the PRBS pattern. Goes

low when synchronized to the PRBS pattern. Any errors in the

received pattern after synchronization will cause a positive going

pulse (with same period as E1 or T1 clock) synchronous with

RCLK. PRBS bit errors can also be reported to the ECR1 and ECR2

registers by setting CCR6.2 to a logic 1.

RCLK

40

O Receive Clock. Buffered recovered clock from the line.

Synchronous to MCLK in absence of signal at RTIP and RRING.

14 of 73

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