DS2155 Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated
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DS2155 Datasheet PDF : 240 Pages
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§ RCL, RLOS, RRA, and RAIS alarms interrupt on
change-of-state
§ Flexible signaling support
– Software or hardware based
– Interrupt generated on change of signaling data
– Receive signaling freeze on loss-of-sync,
carrier loss, or frame slip
§ Addition of hardware pins to indicate carrier loss
and signaling freeze
§ Automatic RAI generation to ETS 300 011
specifications
§ Access to Sa and Si bits
§ Option to extend carrier loss criteria to a 1ms
period as per ETS 300 233
§ Japanese J1 support
– Ability to calculate and check CRC6 according
to the Japanese standard
– Ability to generate Yellow Alarm according to
the Japanese standard
TDM Bus
§ Dual two-frame independent receive and transmit
elastic stores
– Independent control and clocking
– Controlled slip capability with status
– Minimum delay mode supported
§ 16.384MHz maximum backplane burst rate
§ Supports T1 to CEPT (E1) conversion
§ Programmable output clocks for fractional T1, E1,
H0, and H12 applications
§ Interleaving PCM bus operation
§ Hardware signaling capability
– Receive signaling reinsertion to a backplane
multiframe sync
– Availability of signaling in a separate PCM
data stream
– Signaling freezing
§ Ability to pass the T1 F-bit position through the
elastic stores in the 2.048MHz backplane mode
§ Access to the data streams in between the
framer/formatter and the elastic stores
§ User-selectable synthesized clock output
§ Bit-oriented code (BOC) support
HDLC Controllers
§ Two independent HDLC controllers
§ Fast load and unload features for FIFOs
§ SS7 support for FISU transmit and receive
§ Independent 128-byte Rx and Tx buffers with
interrupt support
§ Access FDL, Sa, or single/multiple DS0 channels
§ DS0 access includes Nx64 or Nx56
§ Compatible with polled or interrupt driven
environments
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DS2155
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