DS2155 Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated
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DS2155 Datasheet PDF : 240 Pages
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Test and Diagnostics
§ Programmable on-chip bit error-rate testing
§ Pseudorandom patterns including QRSS
§ User-defined repetitive patterns
§ Daly pattern
§ Error insertion single and continuous
§ Total bit and errored bit counts
§ Payload error insertion
§ Error insertion in the payload portion of the T1
frame in the transmit path
§ Errors can be inserted over the entire frame or
selected channels
§ Insertion options include continuous and absolute
number with selectable insertion rates
§ F-bit corruption for line testing
§ Loopbacks: remote, local, analog, and per-channel
loopback
DS2155
Extended System Information Bus
§ Host can read interrupt and alarm status on up to 8
ports with a single bus read
User-Programmable Output Pins
§ Four user-defined output pins for controlling
external logic
Control Port
§ 8-bit parallel control port
§ Multiplexed or nonmultiplexed buses
§ Intel or Motorola formats
§ Supports polled or interrupt environments
§ Software access to device ID and silicon revision
§ Software reset supported
– Automatic clear on power-up
§ Hardware reset pin
The DS2155 is compliant with the following standards:
ANSI:
T1.403-1995, T1.231–1993, T1.408
AT&T:
TR54016, TR62411
ITU:
G.703, G.704, G.706, G.736, G.775, G.823, G.932, I.431, O.151, Q.161
ITU-T:
Recommendation I.432–03/93 B-ISDN User-Network Interface—Physical Layer
Specification
ETSI:
ETS 300 011, ETS 300 166, ETS 300 233, CTR12, CTR4
Japanese:
JTG.703, JTI.431, JJ-20.11 (CMI Coding Only)
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