DS21552L Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated

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производитель

DS21552L

3.3V DS21352 and 5V DS21552 T1 Single-Chip Transceivers

Dallas Semiconductor -> Maxim Integrated 

DS21352/DS21552

4.1.2 RECEIVE SIDE PINS

Signal Name:

RLINK

Signal Description:

Receive Link Data

Signal Type:

Output

Updated with either FDL data (ESF) or Fs bits (D4) or Z bits (ZBTSI) one RCLK before the start of a frame. See Section 20

for details.

Signal Name:

RLCLK

Signal Description:

Receive Link Clock

Signal Type:

Output

A 4 kHz or 2 kHz (ZBTSI) clock for the RLINK output.

Signal Name:

RCLK

Signal Description:

Receive Clock

Signal Type:

Output

1.544 MHz clock that is used to clock data through the receive side framer.

Signal Name:

RCHCLK

Signal Description:

Receive Channel Clock

Signal Type:

Output

A 192 kHz clock which pulses high during the LSB of each channel. Synchronous with RCLK when the receive side elastic

store is disabled. Synchronous with RSYSCLK when the receive side elastic store is enabled. Useful for parallel to serial

conversion of channel data.

Signal Name:

RCHBLK

Signal Description:

Receive Channel Block

Signal Type:

Output

A user programmable output that can be forced high or low during any of the 24 T1 channels. Synchronous with RCLK when

the receive side elastic store is disabled. Synchronous with RSYSCLK when the receive side elastic store is enabled. Useful for

blocking clocks to a serial UART or LAPD controller in applications where not all T1 channels are used such as Fractional T1,

384K bps service, 768K bps, or ISDN–PRI. Also useful for locating individual channels in drop–and–insert applications, for

external per–channel loopback, and for per–channel conditioning. See Section 13 page 76 for details.

Signal Name:

RSER

Signal Description:

Receive Serial Data

Signal Type:

Output

Received NRZ serial data. Updated on rising edges of RCLK when the receive side elastic store is disabled. Updated on the

rising edges of RSYSCLK when the receive side elastic store is enabled.

Signal Name:

RSYNC

Signal Description:

Receive Sync

Signal Type:

Input/Output

An extracted pulse, one RCLK wide, is output at this pin which identifies either frame (RCR2.4 = 0) or multiframe (RCR2.4 =

1) boundaries. If set to output frame boundaries then via RCR2.5, RSYNC can also be set to output double–wide pulses on

signaling frames. If the receive side elastic store is enabled via CCR1.2, then this pin can be enabled to be an input via RCR2.3

at which a frame or multiframe boundary pulse is applied. See Section 21 for details.

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