DS21552L Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS21552L

3.3V DS21352 and 5V DS21552 T1 Single-Chip Transceivers

Dallas Semiconductor -> Maxim Integrated 

4. PIN FUNCTION DESCRIPTION

DS21352/DS21552

4.1.1 TRANSMIT SIDE PINS

Signal Name:

TCLK

Signal Description:

Transmit Clock

Signal Type:

Input

A 1.544 MHz primary clock. Used to clock data through the transmit side formatter.

Signal Name:

TSER

Signal Description:

Transmit Serial Data

Signal Type:

Input

Transmit NRZ serial data. Sampled on the falling edge of TCLK when the transmit side elastic store is disabled. Sampled on

the falling edge of TSYSCLK when the transmit side elastic store is enabled.

Signal Name:

TCHCLK

Signal Description:

Transmit Channel Clock

Signal Type:

Output

A 192 kHz clock which pulses high during the LSB of each channel. Synchronous with TCLK when the transmit side elastic

store is disabled. Synchronous with TSYSCLK when the transmit side elastic store is enabled. Useful for parallel to serial

conversion of channel data.

Signal Name:

TCHBLK

Signal Description:

Transmit Channel Block

Signal Type:

Output

A user programmable output that can be forced high or low during any of the 24 T1 channels. Synchronous with TCLK when

the transmit side elastic store is disabled. Synchronous with TSYSCLK when the transmit side elastic store is enabled. Useful

for blocking clocks to a serial UART or LAPD controller in applications where not all T1 channels are used such as Fractional

T1, 384 kbps (H0), 768 kbps or ISDN–PRI . Also useful for locating individual channels in drop–and–insert applications, for

external per–channel loopback, and for per–channel conditioning. See section 13 on page 76 for more information.

Signal Name:

TSYSCLK

Signal Description:

Transmit System Clock

Signal Type:

Input

1.544 MHz , 2.048 MHz , 4.096 MHz or 8.192 MHz clock. Only used when the transmit side elastic store function is enabled.

Should be tied low in applications that do not use the transmit side elastic store. See section 20 on page 129 for details on

4.096 MHz and 8.192 MHz operation using the Interleave Bus Option.

Signal Name:

TLCLK

Signal Description:

Transmit Link Clock

Signal Type:

Output

4 kHz or 2 kHz (ZBTSI) demand clock for the TLINK input. See Section 15 for details. Transmit Link Data [TLINK].

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