Table 4-1 PIN DESCRIPTION SORTED BY PIN SYMBOL
PIN
SYMBOL
3
8MCLK
TYPE
O
DESCRIPTION
8.192 MHz Clock
13
8XCLK
66
A0
O
Eight Times Clock
I
Address Bus Bit 0
67
A1
68
A2
69
A3
70
A4
71
A5
I
Address Bus Bit 1
I
Address Bus Bit 2
I
Address Bus Bit 3
I
Address Bus Bit 4
I
Address Bus Bit 5
72
A6
73
ALE (AS)/A7
11
BTS
36
CI
54
CO
75
CS*
56
D0/AD0
57
D1/AD1
I
Address Bus Bit 6
I
Address Latch Enable/Address Bus Bit 7
I
Bus Type Select
I
Carry In
O
Carry Out
I
Chip Select
I/O
Data Bus Bit0/ Address/Data Bus Bit 0
I/O
Data Bus Bit1/ Address/Data Bus Bit 1
58
D2/AD2
59
D3/AD3
I/O
Data Bus Bit 2/Address/Data Bus 2
I/O
Data Bus Bit 3/Address/Data Bus Bit 3
62
D4/AD4
63
D5/AD5
64
D6/AD6
65
D7/AD7
44
DVDD
I/O
Data Bus Bit4/Address/Data Bus Bit 4
I/O
Data Bus Bit 5/Address/Data Bus Bit 5
I/O
Data Bus Bit 6/Address/Data Bus Bit 6
I/O
Data Bus Bit 7/Address/Data Bus Bit 7
–
Digital Positive Supply
81
DVDD
45
DVSS
–
Digital Positive Supply
–
Digital Signal Ground
60
DVSS
–
Digital Signal Ground
80
DVSS
84
DVSS
–
Digital Signal Ground
–
Digital Signal Ground
76
FMS
61
DVDD
83
DVDD
25
INT*
4
JTCLK
I
Framer Mode Select
-
Digital Positive Supply
–
Digital Positive Supply
O
Interrupt
I
IEEE 1149.1 Test Clock Signal
7
JTDI
10
JTDO
I
IEEE 1149.1 Test Data Input
O
IEEE 1149.1 Test Data Output
2
JTMS
5
JTRST
12
LIUC
21
MCLK
55
MUX
8
NC
9
NC
15
NC
I
IEEE 1149.1 Test Mode Select
I
IEEE 1149.1 Test Reset
I
Line Interface Connect
I
Master Clock Input
I
Bus Operation
–
No Connect
–
No Connect
–
No Connect
23
NC
26
NC
–
No Connect
–
No Connect
Table 4-1 PIN DESCRIPTION SORTED BY PIN SYMBOL (cont.)
PIN
SYMBOL
27
NC
28
NC
1
RCHBLK
92
RCHCLK
TYPE
–
–
O
O
DESCRIPTION
No Connect
No Connect
Receive Channel Block
Receive Channel Clock
6
RCL
82
RCLK
O
Receive Carrier Loss
O
Receive Clock
13 of 137
DS21352/DS21552