DAC1617D1G0HN Просмотр технического описания (PDF) - Integrated Device Technology

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DAC1617D1G0HN

Dual 16-bit DAC, LVDS interface, up to 1 Gsps, x2, x4 and x8 interpolating

Integrated Device Technology 

Integrated Device Technology

DAC1617D1G0

Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating

Table 5. Characteristics …continued

VDDA(1V8) = 1.8 V; VDDD = 1.8 V; VDDA(3V3) = 3.3 V; Typical values measured at Tamb = +25 C; RL = 50 ; IO(fs) = 20 mA;

maximum sample rate used; external PLL; no auxiliary DAC; no inverse sinus x/x; no output correction; output load condition

defined in Figure 29; output level = 1 V (p-p).

Symbol

Parameter

Conditions

Test Min

[1]

Typ

Max

Unit

EG

gain error

variation

D

-

INL

integral

non-linearity

D

-

DNL

differential

non-linearity

D

-

Reference voltage output (pin GAPOUT)

VO(ref)

reference output Tamb = +25 C

voltage

I

-

IO(ref)

reference output 1.25 V external voltage

D

-

current

Analog auxiliary outputs (pins AUXAP, AUXAN, AUXBP and AUXBN)

IO(fs)

full-scale output auxiliary DAC A;

I

-

current

differential outputs

auxiliary DAC B;

differential outputs

I

-

VO(aux)

auxiliary output compliance range

voltage

D

0

LVDS input timing

fdata

data rate

fs(max) specification must C

-

be respected

(fs = fdata  interpolation

factor)

tsk(clk-D)

skew time from

clock to data

input

fDATA = 184.32 Mhz

fDATA = 245.76 MHz

fDATA = 307.2 MHz

fDATA = 368.64 MHz

C

800

C

500

C

300

C

150

<tbd>

-

<tbd>

-

<tbd>

-

1.22

-

40

-

3.1

-

3.1

-

-

2.3

-

370

-

830

-

675

-

520

-

500

ppm/C

LSB

LSB

V

A

mA

mA

V

MHz

ps

ps

ps

ps

DAC1617D1G0 3

Preliminary data sheet

Rev. 03 — 2 July 2012

© IDT 2012. All rights reserved.

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