CY7C1329G Просмотр технического описания (PDF) - Cypress Semiconductor
Номер в каталоге
Компоненты Описание
производитель
CY7C1329G Datasheet PDF : 16 Pages
| |||
CY7C1329G
Truth Table[2, 3, 4, 5, 6, 7]
Next Cycle
Unselected
Unselected
Unselected
Unselected
Unselected
Begin Read
Begin Read
Continue Read
Continue Read
Continue Read
Continue Read
Suspend Read
Suspend Read
Suspend Read
Suspend Read
Begin Write
Begin Write
Begin Write
Continue Write
Continue Write
Suspend Write
Suspend Write
ZZ “Sleep”
Add. Used
None
None
None
None
None
External
External
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
External
Next
Next
Current
Current
None
Add. Used
None
None
None
None
None
None
External
External
External
External
External
Next
CE1 CE2 CE3 ZZ ADSP
H
X
XL
X
L
L XL
L
L
X HL
L
L
L XL
H
L
X HL
H
X
X XH
X
L
H
LL
L
L
H LL
L
L
H LL
H
L
H LL
H
L
H LL
H
X
X XL
H
ADSC
L
X
X
L
L
X
X
X
L
L
L
H
ADV WRITE OE
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
H
X
L
X
X
H
L
X
H
H
L
H
L
Next
X
X XL
H
Next
H
X
XL
X
Next
H
X
XL
X
Next
X
X XL
H
Next
H
X
XL
X
Current
X
X XL
H
Current
X
X XL
H
Current
H
X
XL
X
Current
H
X
XL
X
Current
X
X XL
H
H
L
H
H
H
L
H
L
H
L
H
H
H
L
L
X
H
L
L
X
H
H
H
L
H
H
H
H
H
H
H
L
H
H
H
H
H
H
L
X
Truth Table for Read/Write [2, 3]
Read
Function
GW
BWE
BWD
BWC
BWB
BWA
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write Byte A – DQA
Write Byte B – DQB
Write Bytes B, A
H
L
H
H
H
L
H
L
H
H
L
H
H
L
H
H
L
L
Write Byte C – DQC
Write Bytes C, A
H
L
H
L
H
H
H
L
H
L
H
L
Write Bytes C, B
H
L
H
L
L
H
Write Bytes C, B, A
H
L
H
L
L
L
Write Byte D – DQD
Write Bytes D, A
H
L
L
H
H
H
H
L
L
H
H
L
Notes:
2. X = “Don't Care.” H =Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write Enable signals (BWA,BWB,BWC,BWD) and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals
(BWA,BWB,BWC,BWD), BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. CE1, CE2, and CE3 are available only in the TQFP package.
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A:D]. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to Three-State. OE
is a don't care for the remainder of the Write cycle.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are Three-State when
OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05393 Rev. *A
Page 6 of 16
Share Link: 