CY14B101L(2007) Просмотр технического описания (PDF) - Cypress Semiconductor
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CY14B101L Datasheet PDF : 18 Pages
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PRELIMINARY
CY14B101L
AC Switching Characteristics
Parameter
Cypress
Alt.
Parameter Parameter
Description
SRAM Read Cycle
tACE
tRC [9]
tAA [10]
tACS
tRC
tAA
tDOE
tOE
tOHA
tLZCE [11]
tHZCE [11]
tLZOE [11]
tHZOE [11]
tPU [7]
tPD [7]
tOH
tLZ
tHZ
tOLZ
tOHZ
tPA
tPS
SRAM Write Cycle
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold After Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
tWC
tWC
tPWE
tWP
tSCE
tCW
tSD
tDW
tHD
tDH
tAW
tAW
tSA
tAS
tHA
tWR
tHZWE [11, 12] tWZ
tLZWE [11]
tOW
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Data SetUp to End of Write
Data Hold After End of Write
Address SetUp to End of Write
Address SetUp to Start of Write
Address Hold After End of Write
Write Enable to Output Disable
Output Active after End of Write
25 ns part
Min Max
35 ns part
Min Max
45 ns part
Unit
Min Max
25
35
45 ns
25
35
45
ns
25
35
45 ns
12
15
20 ns
3
3
3
ns
3
3
3
ns
10
13
15 ns
0
0
0
ns
10
13
15 ns
0
0
0
ns
25
35
45 ns
25
35
45
ns
20
25
30
ns
20
25
30
ns
10
12
15
ns
0
0
0
ns
20
25
30
ns
0
0
0
ns
0
0
0
ns
10
13
15 ns
3
3
3
ns
Notes
9. WE must be HIGH during SRAM read cycles.
10. Device is continuously selected with CE and OE low.
11. Measured ± 200 mV from steady state output voltage.
12. If WE is low when CE goes low, the outputs remain in the high impedance state.
Document #: 001-06400 Rev. *E
Page 9 of 18
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