CY14B101L(2007) Просмотр технического описания (PDF) - Cypress Semiconductor

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производитель

CY14B101L
(Rev.:2007)

1-Mbit (128K x 8) nvSRAM

Cypress Semiconductor 

PRELIMINARY

Switching Waveforms

SRAM Read Cycle 1(address controlled) [9, 10, 22]

CY14B101L

ADDRESS

DQ (DATA OUT)

tRC

tAA

tOHA

SRAM Read Cycle 2 (CE and OE controlled) [9, 22]

DATA VALID

ADDRESS

CE

OE

DQ (DATA OUT)

ICC

tRC

tLZCE

tACE

tDOE

tLZOE

tPU

STANDBY

ACTIVE

tPD

tHZCE

tHZOE

DATA VALID

Note

22. HSB must remain HIGH during READ and WRITE cycles.

Document #: 001-06400 Rev. *E

Page 11 of 18

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