ACE9050IG Просмотр технического описания (PDF) - Mitel Networks
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ACE9050IG Datasheet PDF : 52 Pages
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EMULATION MODE PROCESSOR INTERFACE
Read and Write Cycles
ACE9050
ECLK
AS
R/W
A[15:8]
A[7:0] / D[7:0]
tCYC
tECLRWV
INVALID
tECLADV
STABLE
tADVASL
AD[7:0]
tASLADI
tECLADI
INVALID
tDAV
tDAI
DA[7:0]
Fig.6 ACE9050 6303 Emulation mode Read/Write cycles timing diagram
Emulation Mode Timing Cycle Conditions
Input clock ECLK frequency = 1·008MHz (Normal clock), 2·016MHz (Turbo clock), TAMB = 125°C, VDD = 15V 610%
Description
Symbol
Normal clock
Min.
Typ.
Max.
Turbo clock
Min.
Typ.
Max.
Units
Cycle time
Read/Write settling time
Address delay time
Address hold time
Address to latch set-up time
Address to latch hold time
Data set-up time - WRITE
Data hold time - WRITE
Data set-up time - READ
Data hold time - READ
tCYC
tECLRWV
tECLADV
tECLADI
tADVASL
tASLADI
tDAV-W
tDAI-W
tDAV-R
tDAI-R
992
496
ns
250
160
ns
250
160
ns
0
0
ns
60
20
ns
30
20
ns
50
50
ns
1
1
ns
80
80
ns
1
1
ns
Table 5 6303 Emulation Mode Read/Write cycles timing
9
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