ACE9050IG Просмотр технического описания (PDF) - Mitel Networks
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ACE9050IG Datasheet PDF : 52 Pages
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ACE9050
Write Cycle (Normal Mode)
ECLK
ADDR
CS
WEN
DATA
tECLK
tADVCSL
tADVWEH
tCSLWEH
tWEHADI
tWELWEH
tWEHCSH
tADVDALZ
tDAVWEH
tWEHDAI
Fig. 5 ACE9050 6303 Write cycle timing diagram
Timing Cycle Conditions
Input clock frequency, XIN = 8·064MHz. Worst case timings: TAMB = 240°C to 185°C, VDD = 13·6V to 15·5V
Typical timings: TAMB = 125°C, VDD = 13·75V
Description
Symbol
Normal clock
Min.
Typ. Max.
Turbo clock
Min.
Typ.
Max.
Cycle time
Address valid to end of Write
Address hold time
Chip enable set-up time
WE pulse width
Data valid set-up time
Data hold time
Address valid to data low Z
Address valid to chip select
WE high to CS high
tECLK
992
tADVWEH
835
853
862
395
tWEHADI
125
140
151
63
tCSLWEH
825
840
860
390
tWELWEH
363
364
371
173
tDAVWEH
365
368
371
177
tWEHDAI
120
60
tADVDALZ
451
473
487
203
tADVCSL
0
5
10
0
tWEHCSH
127
140
163
66
Table 4 ACE9050 6303 Write cycle timing
496
420
427
72
93
415
425
181
184
183
192
225
239
4
9
72
105
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
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