ACE9050IG Просмотр технического описания (PDF) - Mitel Networks
Номер в каталоге
Компоненты Описание
производитель
ACE9050IG Datasheet PDF : 52 Pages
| |||
ACE9050
Pin
Name
Type
Block
Description
Internal
66 KPI [3]
I EPORT
67 KPI [2]
I EPORT
68 KPI [1]
I EPORT
69 KPI [0]
I EPORT
70 INRQ1
I EPORT
71 INRQ0
I EPORT
72 SYNTHDATA
O SINT
73 SYNTHCLK
O SINT
74 SERV
I WDATO
75 LATCH3
O SINT
76 OUTP2 [6]
O EPORT
77 ICN
O (I) IFC
78 LATCH1
O SINT
79 OUTP2[7]
O EPORT
80 LATCH0
O SINT
81 OUTP2[2]/PWM2/ O PWM
LATCH2
82 DTFG
I/O SINT
83 EMUL
I BINT/CPU
84 IRQN
O (I) CPU
85 POFFN
O WDATO
86 VSS
87 VSS
88 VDD
89 EXRESN
O WDATO
90 C1008
O CLK
91 MRN
I WDATO
92 A15
I BINT
93 A14
I BINT
94 CPUCL/OUTP2 [0] O CLK/EPORT
95 R/W
O (I) BINT
96 BAR
O BAR
97 DTMS
I/O CPU
98 OUTP2 [1]/PWM 1 O PWM
99 ECLK
O (I) CLK
100 RXCD
I WDATO
Keypad scan input/input port
Keypad scan input/input port
Keypad scan input/input port
Keypad scan input/input port
External Interrupt (also Bit1 Input Port1)
External Interrupt (also Bit0 Input Port1)
SynthBus Data Line
SynthBus 126kHz Clock
1 = Service Mode
Latch, programmable length. (To ACE9030, LATCHC pin)
Output Port2 Bit 6: High Current Driver
IF Counter Output for Emulation (input in Test mode)
Latch O/P (To ACE9030 receiver Interface, LATCHB pin)
Output Port2 Bit 7: High Current Driver
Latch O/P (To ACE9040, LEN )
Output Port2 Bit 2/Pulse Width Modulator #2 Output/
SynthBus Latch O/P.
Bidirectional serial inter-chip data, to/from the ACE9030
1 = CPU Emulation Mode
CPU Interrupt for Emulation (input in Test mode)
Power On/Off
Ground
Ground
Digital Supply
External reset output
1·008MHz Clock for ACEBus, ACE9030 and ACE9040
0 = Chip reset
Address input for Emulation only
Address input for Emulation only
8.064MHz clock/Out Port 2 bit 0
Read/Write (Input during Emulation)
Beep, Alarm, Ring Tone Output
CPU Port 2 bit 3 or Serial interface (SCI) input
Output Port 2 Bit 1/Pulse Width Modulator #1 Output
Processor Clock (Input during Emulation)
Carrier detect from RX
PD
PD
PD
PD
PD
PD
-
-
None
-
-
PU
-
-
-
-
None
PD
-
-
-
-
-
-
-
None
PU
PU
-
None
-
None
-
None
None
ABBREVIATIONS
BAR
Beep, Alarm and Ring tone generator
BAUD
Baud Rate generator
BINT
Bus Interface
MEMB Memory Bank switching
CLK
Clock generator
CPU
6303 microprocessor unit
DEC
Decoder
EPORT External Port
Table 1 (continued)
I2C
IFC
MODEM
PWM
SINT
WDATO
PU
PD
I2C interface
IF Control counter
AMPS/TACS Modem
Pulse Width Modulator and MUX
Serial Inter-chip interface
Watchdog/Autonomous Time Out
Internal Pullup resistor present
Internal Pulldown resistor present
UNUSED INPUTS
Input or bidirectional pins must have a suitable pullup or pulldown reststor if they are configured as inputs, with no external drive. Some
inputs have an internal pullup or pulldown resistor of the order of 100kΩ; this value is suitable if the pin is not subject to excessive noise
or residual current greater than 15µA. If the pins shown in Table 2 are not used in the system, an external resistor will be required.
Pin
Name
Pin
Name
Pin
Name
4 DFMS
15 P1 [1]
61 TXPOW
7 P1 [7]
16 P1 [0]
74 SERV
8 P1 [6]
51 RXSAT
82 DTFG (Requires
9 P1 [5]
52 INP1 [2]
programming resistor)
12 P1 [4]
53 INP1 [3]
91 MRN
13 P1 [3]
54 INP1 [4]
97 DTMS
14 P1 [2]
60 AFC_IN/RXDATA
100 RXCD
NOTE: P1 [7:0], DFMS and DTMS are configured as inputs upon reset.
Table 2
5
Share Link: 