SAA5265 Просмотр технического описания (PDF) - Philips Electronics

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SAA5265

10 and 1 page intelligent teletext decoders

Philips Electronics 

Philips Semiconductors

10 and 1 page intelligent teletext decoders

Preliminary specification

SAA5264; SAA5265

I2C-BUS CHARACTERISTICS

SYMBOL

PARAMETER

FAST-MODE I2C-bus

MIN.

MAX.

UNIT

fSCL

SCL clock frequency

0

tBUF

bus free time between a STOP and START condition

1.3

400

kHz

−

µs

tHD;STA

hold time START condition; after this period, the first clock 0.6

−

µs

pulse is generated

tLOW

tHIGH

tSU;STA

SCL LOW time

SCL HIGH time

set-up time repeated START

1.3

−

µs

0.6

−

µs

0.6

−

µs

tHD;DAT

tSU;DAT

data hold time; notes 1 and 2

data set-up time; note 3

0

0.9

µs

100

−

ns

tr

rise time SDA and SCL; note 4

20

300

ns

tf

tSU;STO

Cb

fall time SDA and SCL; note 4

set-up time STOP condition

capacitive load of each bus line

20

300

ns

0.6

−

µs

−

400

pF

Notes

1. A device must internally provide a hold time of at least 300 ns for the SDA signal (referenced to the VIHmin of the

SCL signal) in order to bridge the undefined region of the falling edge of SCL.

2. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period of the SCL signal (tLOW(SCL)).

3. A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tSU;DAT ≥250 ns

must then be met. This will automatically be the case if the device does not stretch tLOW(SCL). If such a device does

stretch tLOW(SCL), it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according

to the standard-mode I2C-bus specification) before the SCL line is released.

4. Cb = total capacitance of one bus line in pF.

2000 Jan 27

14

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