RTL8201 Просмотр технического описания (PDF) - Realtek Semiconductor

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RTL8201

REALTEK SINGLE CHIP SINGLE PORT 10/100MBPS FAST ETHERNET PHYCEIVER

Realtek Semiconductor 

RTL8201(L)

6.5. Register 4 Auto-negotiation Advertisement

(ANAR)

This register contains the advertised abilities of this device as they will be transmitted to its link partner during

Auto-negotiation.

Address

Name

Description/Usage

Default/Attribute

4:<15>

NP

Next Page: The RTL8201L does not implement the Next Page function,

0, RO

so bit 15 will always return a ‘0’ when read.

4:<14>

ACK

0: Transmitting the primary capability data page

1: Transmitting the protocol specific data page

Acknowledge: Because the Next Page function is not implemented, bit

14 will always return a ‘0’ when read.

0, RO

4:<13>

1: Acknowledge reception of link partner capability data word

0: Do not acknowledge reception

RF

Remote Fault: Bit 13 returns a value of ‘1’ when the RTL8201L has

0, RW

detected a remote fault. The RTL8201L advertises this information, but

does not act upon it.

4:<12:11>

4:<10>

Reserved

Pause

1: Advertise remote fault detection capability

0: Do not advertise remote fault detection capability

Reserved: Ignore the output of the RTL8201L when these bits are

read.

Pause: The use of this bit is independent of the negotiated data rate,

medium, or link technology. Setting this bit indicates the availability of

additional DTE capabilities when full duplex operation is in use. This

bit is used by one MAC to communicate Pause Capability to its Link

Partner and has no effect on PHY operation.

0, RW

4:<9>

1: Flow control is supported by local node

0: Flow control is NOT supported by local node

T4

100Base-T4: This bit advertises the ability to the Link Partner that the

0, RO

RTL8201L can operate in 100Base-T4 mode. Writing a ‘0’ to this bit

will suppress the transmission of this ability to the Link Partner.

Resetting the chip will restore the default value. The default value is ‘1’

and writing a ‘1’ will set this bit to ‘1’. Reading this bit will return the

last written value or the default value if no write has been completed

since the last reset.

4:<8>

TXFD

1: 100Base-T4 is supported by local node

0: 100Base-T4 not supported by local node

100Base-TX-FD: This bit advertises the ability to the Link Partner that

the RTL8201L can operate in 100Base-TX full duplex mode. Writing a

‘0’ to this bit will suppress the transmission of this ability to the Link

Partner. Resetting the chip will restore the default value. The default

value is ‘1’ and writing a ‘1’ will set this bit to ‘1’. Reading this bit will

return the last written value or the default value if no write has been

completed since the last reset.

1, RW

4:<7>

1: 100Base-TX full duplex is supported by local node

0: 100Base-TX full duplex not supported by local node

TX

100Base-TX: This bit advertises the ability to the Link Partner that the

1, RW

RTL8201L can operate in 100Base-TX half duplex mode. Writing a ‘0’

to this bit will suppress the transmission of this ability to the Link

Partner. Resetting the chip will restore the default value. The default

value is ‘1’ and writing a ‘1’ will set this bit to ‘1’. Reading this bit will

return the last written value or the default value if no write has been

completed since the last reset.

1: 100Base-TX is supported by local node

0: 100Base-TX not supported by local node

2002-01-18

11

Rev.1.04

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