RTL8201 Просмотр технического описания (PDF) - Realtek Semiconductor
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RTL8201 Datasheet PDF : 26 Pages
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RTL8201(L)
6.7 Register 6 Auto-negotiation Expansion (ANER)
This register contains additional status for NWay auto-negotiation.
Address
Name
Description/Usage
Default/Attribute
6:<15:5>
Reserved Reserved: Ignore the output of the RTL8201L when these bits are read.
This bit is always set to 0.
6:<4>
MLF
Multiple Link Fault: Status indicating if a multiple link fault has
0, RO
occurred. Bit 4 is a read-only bit that gets latched high when a multiple
link fault occurs in the Auto-negotiation state machine. For further
details, please consult the IEEE standard. The bit is reset to ‘0’ after the
register is read, or when the chip is reset.
6:<3>
LP_NP_ABLE
1: Fault occurred
0: No fault occurred
Link Partner Next Page Able: Status indicating if the link partner
supports Next Page negotiation. Bit 3 returns a ‘1’ when the Link
Partner has Next Page capabilities. It has the same value as bit 15 of the
Link Partner Ability Register.
0, RO
6:<2>
6:<1>
6:<0>
1: Supported
0: Not supported
NP_ABLE Local Next Page Able: This bit indicates if the local node is able to
send additional Next Pages. The RTL8201L does not have Next Page
capabilities, so it will always return a ‘0’ when bit 2 is read.
PAGE_RX Page Received: This bit is set high when a new Link Code Word Page
has been received from the Link Partner, checked and acknowledged.
This bit is cleared when the link is lost or the chip is reset. It is
automatically cleared when the auto-negotiation link partner’s ability
register (register 5) is read by management.
LP_NW_ABLE Link Partner Auto-Negotiation Able: Bit 0 returns a ‘1’ when the
Link Partner is known to have Auto-negotiation capabilities. Before any
Auto-negotiation information is exchanged, or if the Link Partner does
not comply with IEEE Auto-negotiation, the bit returns a value of ‘0’.
0, RO
0, RO
0, RO
1: Link partner supports Nway auto-negotiation
0: Link partner does not support Nway auto-negotiation
6.8 Register 16 Nway Setup (NSR)
Address
16:<15:12>
16:<11>
16:<10>
16:<9>
16:<8:3>
16:<2>
16:<1>
16:<0>
Name
Reserved
ENNWLE
Testfun
NWLPBK
Reserved
FLAGABD
FLAGPDF
FLAGLSC
Description/Usage
Ignore the results of these bits when read.
1: LED4 Pin indicates linkpulse
1: Auto-neg speeds up internal timer
1: Set Nway to loopback mode.
Ignore the results of these bits when read.
1: Auto-neg experienced ability detect state
1: Auto-neg experienced parallel detection fault state
1: Auto-neg experienced link status check state
Default/Attribute
0, RW
0, RW
0, RW
0, RO
0, RO
0, RO
2002-01-18
14
Rev.1.04
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