ATMEGA323 Просмотр технического описания (PDF) - Atmel Corporation

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ATMEGA323

8-bit Microcontroller with 32K Bytes of In-System Programmable Flash

Atmel Corporation 

Table 2. ATmega323 I/O Space (Continued)

I/O Address (SRAM

Address)

Name

Function

$12 ($32)

PORTD Data Register, Port D

$11 ($31)

DDRD

Data Direction Register, Port D

$10 ($30)

PIND

Input Pins, Port D

$0F ($2F)

SPDR

SPI I/O Data Register

$0E ($2E)

SPSR

SPI Status Register

$0D ($2D)

SPCR

SPI Control Register

$0C ($2C)

UDR

USART I/O Data Register

$0B ($2B)

UCSRA USART Control and Status Register A

$0A ($2A)

UCSRB USART Control and Status Register B

$09 ($29)

UBRRL USART Baud Rate Register Low Byte

$08 ($28)

ACSR

Analog Comparator Control and Status Register

$07 ($27)

ADMUX ADC Multiplexer Select Register

$06 ($26)

ADCSR ADC Control and Status Register

$05 ($25)

ADCH

ADC Data Register High

$04 ($24)

ADCL

ADC Data Register Low

$03 ($23)

TWDR

Two-wire Serial Interface Data Register

$02 ($22)

TWAR

Two-wire Serial Interface (Slave) Address Register

$01 ($21)

TWSR

Two-wire Serial Interface Status Register

$00 ($20)

TWBR

Two-wire Serial Interface Bit Rate Register

Notes:

1. When the OCDEN Fuse is unprogrammed, the OSCCAL Register is always

accessed on this address. Refer to the debugger specific documentation for details

on how to use the OCDR Register.

2. Refer to the USART description for details on how to access UBRRH and UCSRC.

All ATmega323 I/Os and peripherals are placed in the I/O space. The I/O locations are

accessed by the IN and OUT instructions, transferring data between the 32 general pur-

pose working registers and the I/O space. I/O Registers within the address range $00 -

$1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the

value of single bits can be checked by using the SBIS and SBIC instructions. Refer to

the instruction set chapter for more details. When using the I/O specific commands IN

and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O Registers as

SRAM, $20 must be added to these addresses. All I/O Register addresses throughout

this document are shown with the SRAM address in parentheses.

For compatibility with future devices, reserved bits should be written to zero if accessed.

Reserved I/O Memory addresses should never be written.

Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI

and SBI instructions will operate on all bits in the I/O Register, writing a one back into

any flag read as set, thus clearing the flag. The CBI and SBI instructions work with reg-

isters $00 to $1F only.

The I/O and Peripherals Control Registers are explained in the following sections.

20 ATmega323(L)

1457G–AVR–09/03

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