ADN2865 Просмотр технического описания (PDF) - Analog Devices
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производитель
ADN2865
Analog Devices
ADN2865 Datasheet PDF : 33 Pages
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Preliminary Technical Data
Table 5. Pin Function Descriptions
Pin # Mnemonic
1
SDOUT
2
RXDATN1
3
RXDATP1
4
RXDATN0
5
RXDATP0
6
VCC3
7
VCC7
8
SERDATN
9
SERDATP
10
SERCLKN
11
SERCLKP
12
TXDAT7
13
TXDAT6
14
TXDAT5
15
TXDAT4
16
TXCLK
17
TXDAT3
18
TXDAT2
19
TXDAT1
20
TXDAT0
21
VREG
22
CF1
23
VEE2
24
VCC2
25
VEE4
26
VCC4
27
REFN
28
REFP
29
THRADJ
30
LOL
31
VEE1
32
SLICEN
33
SLICEP
34
NIN
35
PIN
36
VREF
37
VCC1
38
SCK
39
VCC6
40
SDA
41
RXCLKN
42
RXCLKP
43
RXDATN7
44
RXDATP7
45
VCC5
46
RXDATN6
47
RXDATP6
48
RXDATN5
49
RXDATP5
50
VCC5
51
RXDATN4
52
RXDATP4
53
RXDATN3
54
RXDATP3
55
RXDATN2
56
RXDATP2
Type
DO
DO
DO
DO
DO
PWR
PWR
DO
DO
DO
DO
DI
DI
DI
DI
DI
DI
DI
DI
DI
AO
AO
PWR
PWR
PWR
PWR
DI
DI
AO
DO
PWR
AI
AI
AI
AI
AO
PWR
DI
PWR
DI
DO
DO
DO
DO
PWR
DO
DO
DO
DO
PWR
DO
DO
DO
DO
DO
DO
Description
Active high, Loss of signal indicator. (LVTTL)
Differential receive data output. (LVDS)
Differential receive data output. (LVDS)
Differential receive data output. Last bit received. (LVDS)
Differential receive data output. Last bit received. (LVDS)
Power for CDR & Serialiser
Power for CML drivers
Differential serialized data output to LDD. (CML)
Differential serialized data output to LDD. (CML)
Differential clock for serialized Tx data. (CML)
Differential clock for serialized Tx data. (CML)
Transmit data input. First bit sent. (LVTTL)
Transmit data input. (LVTTL)
Transmit data input. (LVTTL)
Transmit data input. (LVTTL)
Qualifying clock for transmit data input. (LVTTL)
Transmit data input. (LVTTL)
Transmit data input. (LVTTL)
Transmit data input. (LVTTL)
Transmit data input. Last bit sent. (LVTTL)
Decoupling node for VCO power.
PLL loop filter capacitor.
Ground for VCO / PLL / Gm
Power for VCO / PLL / Gm
Ground for FLL
Power for FLL
Reference clock input. (LVDS/LVTTL)
Reference clock input. (LVDS/LVTTL)
LOS Threshold Setting Resistor.
Active high, Loss-of-Lock Indicator. (LVTTL)
Ground for Limamp / LOS
Differential Slice Level Adjust Input.
Differential Slice Level Adjust Input.
Differential serial input to Limiting Amp. (CML)
Differential serial input to Limiting Amp. (CML)
Decoupling node for internal voltage reference.
Power for Limamp / LOS
I2C Serial Clock Input.
Power for Deserialiser, LVDS pre-drivers
I2C Serial Data Input.
Qualifying clock for Rx Data Outputs. (LVDS)
Qualifying clock for Rx Data Outputs. (LVDS)
Differential receive data output. Last bit received. (LVDS)
Differential receive data output. Last bit received. (LVDS)
Power for LVDS drivers
Differential receive data output. (LVDS)
Differential receive data output. (LVDS)
Differential receive data output. (LVDS)
Differential receive data output. (LVDS)
Power for LVDS Drivers
Differential receive data output. (LVDS)
Differential receive data output. (LVDS)
Differential receive data output. (LVDS)
Differential receive data output. (LVDS)
Differential receive data output. (LVDS)
Differential receive data output. (LVDS)
1Type: P = power, AI = analog input, AO = analog output, DI = digital input, DO = digital output.
Rev. PrA | Page 11 of 33
ADN2865
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