ADN2865 Просмотр технического описания (PDF) - Analog Devices

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производитель

ADN2865

Continuous Rate 12.3Mb/s to 2.7Gb/s Clock and Data Recovery IC w/Loop Timed SERDES

Analog Devices 

Preliminary Technical Data

ADN2865

Table 13. FDDI_MODE

FDDI Enable

D7

0= FDDI Mode Disabled

1= FDDI Mode Enabled

Subharmonic Ratio [6..2]

D6 D5 D4 D3 D2

0 0 0 0 1 =1

0 0 0 1 0 =2

0 0 0 1 1 =3

---------------------

1 1 1 1 1 = 31

D1

Set to 0

D0

Set to 0

Table 14. SEL_MODE

Mode Control 2 Mode Control 1

Mode Control 0

Clock Holdover

Mode 2A

Clock Holdover

Mode 2B

D7 D6 D5

D4

D3

D2

D1

D0

Set Set 0=LTD/LTR Mode 0= Continuous Rate 0= Full Range (12.3M- Set to 1 for Clock

Set to 1 for Clock

Set

to 0 to 0 1=LTR Mode Only 1= Single Rate

2.7G)

Holdover Mode 2A Holdover Mode 2B to 0

1= Limited Range

Table 15. CTLF

D7

D6

D5

Set to 0 Set to 0 Set to 0

D4

Set to 0

D3

Set to 0

CDR Mode

D2 D1 D0

0 0 0 = NDC -> OB

1 0 1 = NDC -> PRBS

Rev. PrA | Page 15 of 33

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