ADF41020BCPZ-RL7(Rev0) Просмотр технического описания (PDF) - Analog Devices
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ADF41020BCPZ-RL7 Datasheet PDF : 16 Pages
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ADF41020
Data Sheet
THEORY OF OPERATION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 9. SW1 and SW2
are normally closed switches. SW3 is a normally open switch.
When power-down is initiated, SW3 is closed and SW1 and
SW2 are opened. This ensures that there is no loading of the
REFIN pin on power-down.
POWER-DOWN
CONTROL
NC 100kΩ
SW2
REFIN
NC
SW1
SW3
NO
TO R COUNTER
BUFFER
Figure 9. Reference Input Stage
RF INPUT STAGE
The RF input stage is shown in Figure 10. It is followed by a
buffer, which generates the differential CML levels needed for
the prescaler.
AVDD
RFIN
3pF
50Ω
BUFFER
TO DIVIDE BY 4
PRESCALER
GND
Figure 10. RF Input Stage
PRESCALER
The ADF41020 uses a two prescaler approach to achieve
operation up to 18 GHz. The first prescaler is a fixed
divide-by-4 block. The second prescaler, which takes its
input from the divide-by-4 output, is implemented as a dual-
modulus prescaler (P/P + 1), which allows finer frequency
resolution vs. a fixed prescaler. Along with the A counter and
B counter, this enables the large division ratio, N, to be realized
(N = 4(BP + A)). The dual-modulus prescaler, operating at
CML levels, takes the clock from the fixed prescaler stage and
divides it down to a manageable frequency for the CMOS A
counter and B counter. The second prescaler is programmable.
It can be set in software to 8/9, 16/17, 32/33, or 64/65. It is
based on a synchronous 4/5 core. There is a minimum divide
ratio possible for contiguous output frequencies. This minimum
is given by 4(P2 − P).
A COUNTER AND B COUNTER
The A counter and B counter combine with the two prescalers
to allow a wide ranging division ratio in the PLL feedback
counter. The counters are specified to work when the prescaler
output is 350 MHz or less.
Pulse Swallow Function
Because of the fixed divide-by-4 block, the generated output
frequencies are spaced by four times the reference frequency
divided by R. The equation for VCO frequency is
fVCO
(P
B)
A
4
f REFIN
R
where:
fVCO is the output frequency of the external voltage controlled
oscillator (VCO).
P is the preset modulus of the dual-modulus prescaler
(such as, 8/9, 16/17).
B is the preset divide ratio of the binary 13-bit counter
(2 to 8191).
A is the preset divide ratio of the binary 6-bit swallow
counter (0 to 63).
fREFIN is the external reference frequency oscillator.
N = 4(BP + A)
FROM RF INPUT
BUFFER
DIVIDE BY 4
PRESCALER
P/P + 1
MODULUS
CONTROL
13-BIT B
COUNTER
LOAD
LOAD
6-BIT A
COUNTER
TO PFD
N DIVIDER
Figure 11. Prescalers, A and B Counters that Make Up the N-Divide Value
Rev. 0 | Page 8 of 16
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