ADF41020BCPZ-RL7(Rev0) Просмотр технического описания (PDF) - Analog Devices
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ADF41020BCPZ-RL7 Datasheet PDF : 16 Pages
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ADF41020
Data Sheet
Parameter
Min
NOISE CHARACTERISTICS
Normalized Phase Noise Floor4
Normalized 1/f Noise5
Phase Noise Performance6
5.7 GHz
12.5 GHz7
17.64 GHz
Spurious Signals
5.7 GHz
12.5 GHz7
17.64 GHz
Typ
Max Unit Test Conditions/Comments
−221
−118
−89
−82
−96
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
PLL loop bandwidth = 500 kHz
Normalized to 10 kHz offset at 1 GHz
At VCO output
At 1 kHz offset and 2.5 MHz PFD frequency with
20 kHz loop bandwidth
At 3 kHz offset and 2.5 MHz PFD frequency with
20 kHz loop bandwidth
At 100 kHz offset and 90 MHz PFD frequency with
700 kHz loop bandwidth
−80/−86
−98/<−110
−109/−113
dBc
At 2.5 MHz/5 MHz and 2.5 MHz PFD frequency
dBc
At 2.5 MHz/5 MHz and 2.5 MHz PFD frequency
dBc
At 90 MHz/180 MHz and 90 MHz PFD frequency
1 This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that
is less than this value.
2 Guaranteed by design. Sample tested to ensure compliance.
3 TA = 25°C; AVDD = DVDD = VP = 3.0 V; P = 16; fREFIN = 100 MHz; fPFD = 100 MHz; RFIN = 12.8 GHz.
4 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider
value) and 10 log fPFD. PNSYNTH = PNTOT − 10 log fPFD − 20 log N.
5 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, fRF,
and at a frequency offset, f, is given by PN = PN1_f + 10 log(10 kHz/f) + 20 log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in
ADIsimPLL.
6 The phase noise is measured with a Rohde & Schwarz FSUP spectrum analyzer. The reference is provided by a Rohde & Schwarz SMA100A.
7 The phase noise and spurious noise is measured with the EV-ADF41020EB1Z evaluation board and the Rohde & Schwarz FSUP spectrum analyzer.
TIMING CHARACTERISTICS
AVDD = DVDD = VP = 3.0 V, GND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMAX to TMIN, unless otherwise noted.
Table 2.
Parameter
t1
t2
t3
t4
t5
t6
Limit
10
10
25
25
10
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
DATA to CLK setup time
DATA to CLK hold time
CLK high duration
CLK low duration
CLK to LE setup time
LE pulse width
t3
t4
CLK
DATA DB23 (MSB)
t1
t2
DB22
LE
LE
DB2
DB1 (CONTROL
BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t6
t5
Figure 2. Timing Diagram
Rev. 0 | Page 4 of 16
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