AD9864 Просмотр технического описания (PDF) - Analog Devices
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AD9864 Datasheet PDF : 44 Pages
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AD9864
AD9864 SPECIFICATIONS
Table 1. VDDI = VDDF = VDDA = VDDC = VDDL = VDDH = 2.7 V to 3.6 V, VDDQ = VDDP = 2.7 V to 5.5 V, fCLK = 18 MSPS,
fIF = 109.65 MHz, fLO = 107.4 MHz, fREF = 16.8 MHz, unless otherwise noted. Standard operating mode: VGA at minimum attenuation
setting, synthesizers in normal (not fast acquire) mode, decimation factor = 900, 16-bit digital output, and 10 pF load on SSI output pins.
Parameter
Temperature Test Level Min Typ
Max
Unit
SYSTEM DYNAMIC PERFORMANCE1
SSB Noise Figure @ Minimum VGA Attenuation2, 3
Full
IV
7.5
9.5
dB
@ Maximum VGA Attenuation2,3
Full
IV
13
dB
Dynamic Range with AGC Enabled2,3
Full
IV
91 95
dB
IF Input Clip Point @ Maximum VGA Attenuation3
Full
IV
–20 –19
dBm
@ Minimum VGA Attenuation3
Full
IV
–32 –31
dBm
Input Third Order Intercept (IIP3)
Full
IV
–12 –7.0
dBm
Gain Variation over Temperature
Full
IV
0.7
2
dB
LNA + MIXER
Maximum RF and LO Frequency Range
LNA Input Impedance
Mixer LO Input Resistance
Full
IV
300 500
25°C
V
370||1.4
25°C
V
1
MHz
Ω||pF
kΩ
LO SYNTHESIZER
LO Input Frequency
Full
IV
7.75
300
MHz
LO Input Amplitude
Full
IV
0.3
2.0
V p-p
FREF Frequency (for Sinusoidal Input Only)
FREF Input Amplitude
FREF Slew Rate
Minimum Charge Pump Current @ 5 V4
Maximum Charge Pump Current @ 5 V4
Charge Pump Output Compliance5
Synthesizer Resolution
Full
IV
8
25
MHz
Full
IV
0.3
3
V p-p
Full
IV
7.5
V/µs
Full
VI
0.67
mA
Full
VI
5.3
mA
Full
VI
0.4
VDDP – 0.4 V
Full
IV
6.25
kHz
CLOCK SYNTHESIZER
CLK Input Frequency
Full
IV
13
26
MHz
CLK Input Amplitude
Minimum Charge Pump Output Current4
Maximum Charge Pump Output Current4
Charge Pump Output Compliance5
Synthesizer Resolution
Full
IV
0.3
VDDC
V p-p
Full
VI
0.67
mA
Full
VI
5.3
mA
Full
VI
0.4
VDDQ – 0.4 V
Full
VI
2.2
kHz
Σ-∆ ADC
Resolution
Clock Frequency (fCLK)
Center Frequency
Pass-Band Gain Variation
Full
IV
16
24
Bits
Full
IV
13
26
MHz
Full
V
fCLK/8
MHz
Full
IV
1.0
dB
Alias Attenuation
Full
IV
80
dB
GAIN CONTROL
Programmable Gain Step
AGC Gain Range
GCP Output Resistance
Full
V
16
dB
Full
V
12
dB
Full
IV
50 72.5
95
kΩ
1 This includes 0.9 dB loss of matching network.
2 AGC with DVGA enabled.
3 Measured in 10 kHz bandwidth.
4 Programmable in 0.67 mA steps.
5 Voltage span in which LO (or CLK) charge pump output current is maintained within 5% of nominal value of VDDP/2 (or VDDQ/2).
Rev. 0 | Page 4 of 44
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