AD9864 Просмотр технического описания (PDF) - Analog Devices
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AD9864 Datasheet PDF : 44 Pages
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AD9864
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
48 47 46 45 44 43 42 41 40 39 38 37
MXOP 1
MXON 2
GNDF 3
IF2N 4
IF2P 5
VDDF 6
GCP 7
GCN 8
VDDA 9
GNDA 10
VREFP 11
VREFN 12
PIN 1
IDENTIFIER
AD9864
TOP VIEW
(Not to Scale)
36 GNDL
35 FREF
34 GNDS
33 SYNCB
32 GNDH
31 FS
30 DOUTB
29 DOUTA
28 CLKOUT
27 VDDH
26 VDDD
25 PE
13 14 15 16 17 18 19 20 21 22 23 24
Figure 2. 48-Lead LFCSP, Backside Paddle Contact Is Connected to Ground
Table 5. Pin Function Descriptions—48-Lead Lead Frame Chip Scale Package (LFCSP)
Pin No. Mnemonic Description
Pin No. Mnemonic
1
MXOP
Mixer Output, Positive
27
VDDH
2
MXON
Mixer Output, Negative
28
CLKOUT
3
GNDF
Ground for Front End of ADC
29
DOUTA
4
IF2N
Second IF Input (to ADC), Negative
30
DOUTB
5
IF2P
Second IF Input (to ADC), Positive
6
VDDF
Positive Supply for Front End of ADC
7
GCP
Filter Capacitor for ADC Full-Scale
Control
31
FS
32
GNDH
33
SYNCB
8
GCN
Full-Scale Control Ground
9
VDDA
Positive Supply for ADC Back End
10
GNDA
Ground for ADC Back End
34
GNDS
35
FREF
11
VREFP
Voltage Reference, Positive
12
VREFN
Voltage Reference, Negative
13
RREF
Reference Resistor: Requires 100 kΩ to
GNDA
14
VDDQ
Positive Supply for Clock Synthesizer
36
GNDL
37
GNDP
38
IOUTL
15
IOUTC
Clock Synth Charge Pump Out Current
16
GNDQ
Ground for Clock Synthesizer Charge
Pump
17
VDDC
Positive Supply for Clock Synthesizer
18
GNDC
Ground for Clock Synthesizer
39
VDDP
40
VDDL
41
CXVM
19
CLKP
Sampling Clock Input/Clock VCO Tank,
Positive
42
LON
20
CLKN
Sampling Clock Input/Clock VCO Tank,
Negative
43
LOP
21
GNDS
Substrate Ground
22
GNDD
Ground for Digital Functions
44
CXVL
23
PC
Clock Input for SPI Port
45
GNDI
24
PD
Data I/O for SPI Port
46
CXIF
25
PE
Enable Input for SPI Port
26
VDDD
Positive Supply for Internal Digital
47
IFIN
48
VDDI
Description
Positive Supply for Digital Interface
Clock Output for SSI Port
Data Output for SSI Port
Data Output for SSI Port (Inverted) or
SPI Port
Frame Sync for SSI Port
Ground for Digital Interface
Resets SSI and DecimatorCounters;
Active Low
Substrate Ground
Reference Frequency Input for Both
Synthesizers
Ground for LO Synthesizer
Ground for LO Synthesizer Charge
Pump
LO Synthesizer Charge Pump Out
Current
Positive Supply for LO Synthesizer
Charge Pump
Postive Supply for LO Synthesizer
External Filter Capacitor; DC Output of
LNA
LO Input to Mixer and LO Synthesizer,
Negative
LO Input to Mixer and LO Synthesizer,
Positive
External Bypass Capacitor for LNA
Power Supply
Ground for Mixer and LNA
External Capacitor for Mixer V-I
Converter Bias
First IF Input (to LNA)
Positive Supply for LNA and Mixer
Rev. 0 | Page 8 of 44
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