AD9848 Просмотр технического описания (PDF) - Analog Devices

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AD9848

CCD Signal Processors with Integrated Timing Driver

Analog Devices 

AD9848/AD9849

PRECISION TIMING HIGH-SPEED TIMING

GENERATION

The AD9848 and AD9849 generate flexible high-speed timing

signals using the Precision Timing core. This core is the founda-

tion for generating the timing used for both the CCD and the

AFE; the reset gate RG, horizontal drivers H1–H4, and the

SHP/SHD sample clocks. A unique architecture makes it

routine for the system designer to optimize image quality, by

providing precise control over the horizontal CCD readout

and the AFE correlated double sampling.

Timing Resolution

The Precision Timing core uses a 1X master clock input (CLI) as

a reference. This clock should be the same as the CCD pixel

clock frequency. Figure 4 illustrates how the internal timing core

divides the master clock period into 48 steps or edge positions.

Therefore, the edge resolution of the Precision Timing core is

(tCLI/48). For more information on using the CLI input, see the

Application Information section.

High Speed Clock Programmability

Figure 5 shows how the high-speed clocks RG, H1–H4, SHP,

and SHD are generated. The RG pulse has programmable rising

and falling edges, and may be inverted using the polarity control.

The horizontal clocks H1 and H3 have programmable rising and

falling edges, and polarity control. The H2 and H4 clocks are

always inverses of H1 and H3 respectively. Table II summarizes

the high-speed timing registers and their parameters.

The edge location registers are 6 bits wide, but there are only

48 valid edge locations available. Therefore, the register values

are mapped into four quadrants, with each quadrant containing

12 edge locations. Table III shows the correct register values

for the corresponding edge locations. Figure 6 shows the range

and default locations of the high-speed clock signals.

POSITION

P[0]

CLI

tCLIDLY

1 PIXEL

PERIOD

P[12]

...

P[24]

P[36]

P[48]=P[0]

...

NOTES

1. PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH-SPEED CLOCKS.

2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITIONS (tCLIDLY = 6 ns TYP).

Figure 4. High-Speed Clock Resolution From CLI Master Clock Input

(3)

CCD SIGNAL

(4)

(1)

(2)

RG

(5)

(6)

H1/H3

H2/H4

NOTES

PROGRAMMABLE CLOCK POSITIONS:

(1) RG RISING EDGE AND (2) FALLING EDGE

(3) SHP AND (4) SHD SAMPLE LOCATION

(5) H1/H3 RISING EDGE POSITION AND (6) FALLING EDGE POSITION (H2/H4 ARE INVERSE OF H1/H3)

Figure 5. High-Speed Clock Programmable Locations

REV. 0

–19–

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