AD9540BCPZ-REEL7(RevC) Просмотр технического описания (PDF) - Analog Devices
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AD9540BCPZ-REEL7 Datasheet PDF : 32 Pages
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Data Sheet
655 MHz Low Jitter Clock Generator
AD9540
FEATURES
Excellent intrinsic jitter performance
200 MHz phase frequency detector inputs
655 MHz programmable input dividers for the phase
frequency detector (÷M, ÷N) {M, N = 1 to 16} (bypassable)
Programmable RF divider (÷R) {R = 1, 2, 4, 8} (bypassable)
8 programmable phase/frequency profiles
400 MSPS internal DDS clock speed
48-bit frequency tuning word resolution
14-bit programmable phase offset
1.8 V supply for device operation
3.3 V supply for I/O, CML driver, and charge pump output
Software controlled power-down
48-lead LFCSP package
Programmable charge pump current (up to 4 mA)
Dual-mode PLL lock detect
655 MHz CML-mode PECL-compliant output driver
APPLICATIONS
Clocking high performance data converters
Base station clocking applications
Network (SONET/SDH) clocking
Gigabit Ethernet (GbE) clocking
Instrumentation clocking circuits
Agile LO frequency synthesis
Automotive radar
FM chirp source for radar and scanning systems
Test and measurement equipment
Acousto-optic device drivers
FUNCTIONAL BLOCK DIAGRAM
AVDD AGND DVDD DGND CP_VDD
CP_RSET
REFIN
REFIN
SYNC_IN/STATUS
CLK1
CLK1
SCLK
SDI/O
SDO
CS
S2
S1
S0
SYNC, PLL
LOCK
M DIVIDER
N DIVIDER
PHASE
FREQUENCY
DETECTOR
CP
REF, AMP
CHARGE
PUMP
DIVIDER
1, 2, 4, 8
SERIAL
CONTROL
PORT
TIMING AND
CONTROL LOGIC
PHASE/
FREQUENCY
PROFILES
CML
CLK
DIVCLK
48
14
AD9540
DDS 10
DAC
CP_OUT
CLK2
CLK2
DRV_RSET
OUT0
OUT0
IOUT
IOUT
Figure 1.
DAC_RSET
Rev. C
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