AD9540BCPZ-REEL7(RevC) Просмотр технического описания (PDF) - Analog Devices
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AD9540BCPZ-REEL7 Datasheet PDF : 32 Pages
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Data Sheet
AD9540
Parameter
I/O_Update to SYNC_OUT Setup Time
PS[2:0> to SYNC_OUT Setup Time
Latencies/Pipeline Delays
I/O_Update to DAC Frequency Change
I/O_Update to DAC Phase Change
PS[2:0] to DAC Frequency Change
PS[2:0] to DAC Phase Change
I/O_Update to CP_OUT Scaler Change
I/O_Update to Frequency Accumulator
Step Size Change
DAC OUTPUT CHARACTERISTICS
Resolution
Full-Scale Output Current
Gain Error
Output Offset
Output Capacitance
Voltage Compliance Range
Wideband SFDR (DC to Nyquist)
10 MHz Analog Out
40 MHz Analog Out
80 MHz Analog Out
120 MHz Analog Out
160 MHz Analog Out
Narrow-Band SFDR
10 MHz Analog Out (±1 MHz)
10 MHz Analog Out (±250 kHz)
10 MHz Analog Out (±50 kHz)
40 MHz Analog Out (±1 MHz)
40 MHz Analog Out (±250 kHz)
40 MHz Analog Out (±50 kHz)
80 MHz Analog Out (±1 MHz)
80 MHz Analog Out (±250 kHz)
80 MHz Analog Out (±50 kHz)
120 MHz Analog Out (±1 MHz)
120 MHz Analog Out (±250 kHz)
120 MHz Analog Out (±50 kHz)
160 MHz Analog Out (±1 MHz)
160 MHz Analog Out (±250 kHz)
160 MHz Analog Out (±50 kHz)
DAC RESIDUAL PHASE NOISE
19.7 MHz FOUT
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
>1 MHz Offset
Min
Typ Max
7
7
33
33
29
29
4
4
Unit
Test Conditions/Comments
ns
ns
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
10
10
−10
5
AVDD − 0.50
65
62
57
56
54
83
85
86
82
84
87
80
82
86
80
82
84
80
82
84
Bits
15
mA
+10
% fS
0.6
µA
pF
AVDD + 0.50
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
122
dBc/Hz
134
dBc/Hz
143
dBc/Hz
150
dBc/Hz
158
dBc/Hz
160
dBc/Hz
Rev. C | Page 7 of 32
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