AD80066KRSZRL(RevA) Просмотр технического описания (PDF) - Analog Devices

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производитель

AD80066KRSZRL
(Rev.:RevA)

Complete 16-Bit CCD/CIS Signal Processor

Analog Devices 

AD80066

ANALOG

INPUTS

CDSCLK2

ADCCLK

OUTPUT

DATA

(D[7:0])

PIXEL (n – 4)

HIGH BYTE

PIXEL n

tAD

tC2

PIXEL (n + 1)

tPRB

tC2ADR

tADCCLK

PIXEL (n – 4)

LOW BYTE

tC2ADF

tADCCLK

tOD

PIXEL (n – 3)

HIGH BYTE

PIXEL (n – 3)

LOW BYTE

Figure 8. 1-Channel SHA Mode Timing

PIXEL (n – 2)

HIGH BYTE

PIXEL (n – 2)

LOW BYTE

ADCCLK

OUTPUT DATA

(D[7:0])

HIGH BYTE

(DB[15:8])

PIXEL n

tOD

tOD

LOW BYTE

(DB[7:0])

HIGH BYTE

(DB[15:8])

LOW BYTE

(DB[7:0])

PIXEL n

PIXEL (n + 1)

PIXEL (n + 1)

Figure 9. Digital Output Data Timing

LOW BYTE

(DB[7:0])

PIXEL (n + 2)

HIGH BYTE

(DB[15:8])

PIXEL (n + 3)

ADCCLK

tOD

OUTPUT DATA

(D[7:0])

HIGH BYTE

(DB[15:8])

HIGH BYTE

(DB[15:8])

PIXEL n

PIXEL (n + 1)

Figure 10. Single-Byte Mode Digital Output Data Timing

HIGH BYTE

(DB[15:8])

PIXEL (n + 2)

SDATA

SCLK

SLOAD

R/W

A3 A2 A1 A0

tDH

tDS

D8 D7 D6

D5 D4

D3 D2 D1 D0

tLS

tLH

Figure 11. Serial Write Operation Timing

SDATA

SCLK

SLOAD

R/W A3

A2

A1

A0

D8 D7 D6 D5 D4 D3 D2 D1 D0

tRDV

tL S

tLH

Figure 12. Serial Read Operation Timing

Rev. A | Page 8 of 20

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