AD80066KRSZRL(RevA) Просмотр технического описания (PDF) - Analog Devices

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AD80066KRSZRL
(Rev.:RevA)

Complete 16-Bit CCD/CIS Signal Processor

Analog Devices 

AD80066

SPECIFICATIONS

ANALOG SPECIFICATIONS

TMIN to TMAX, AVDD = 5 V, DRVDD = 5 V, CDS mode, fADCCLK = 24 MHz, fCDSCLK1 = fCDSCLK2 = 6 MHz, PGA gain = 1, unless otherwise noted.

Table 1.

Parameter

MAXIMUM CONVERSION RATE

4-Channel Mode with CDS

3-Channel Mode with CDS

2-Channel Mode with CDS

1-Channel Mode with CDS

ACCURACY (ENTIRE SIGNAL PATH)

ADC Resolution

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

No Missing Codes

ANALOG INPUTS

Input Signal Range1

Allowable Reset Transient1

Input Limits2

Input Capacitance

Input Bias Current

AMPLIFIERS

PGA Gain Range

PGA Gain Resolution2

PGA Gain Monotonicity

Programmable Offset Range

Programmable Offset Resolution

Programmable Offset Monotonicity

NOISE AND CROSSTALK

Total Output Noise at PGA Minimum

Total Output Noise at PGA Maximum

Channel-to-Channel Crosstalk

@ 24 MSPS

@ 12 MSPS

POWER SUPPLY REJECTION

AVDD = 5 V ± 0.25 V

VOLTAGE REFERENCE (TA = 25°C)

CAPT − CAPB

TEMPERATURE RANGE

Operating

Storage

POWER SUPPLIES

AVDD

DRVDD

OPERATING CURRENT

AVDD

DRVDD

Power-Down Mode Current

Min

AVSS − 0.3

1

−305

0

−65

4.5

3.0

Typ

24

24

24

12

16

+20/−5

±0.5

Guaranteed

1.5/3.0

2.0

10

10

64

Guaranteed

512

Guaranteed

9.5

35

70

90

0.1

0.75

5.0

3.3

95

4

300

Max

AVDD + 0.3

5.9

+295

70

+150

5.25

5.25

Unit

MSPS

MSPS

MSPS

MSPS

Bits

LSB

LSB

V p-p

V

V

pF

nA

V/V

Steps

mV

Steps

LSB rms

LSB rms

dB

dB

% FSR

V

°C

°C

V

V

mA

mA

μA

Rev. A | Page 3 of 20

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