• External Data Access Timing (XCS0, DCS0 to 5/no data wait)
(1) Read (byte access/no data wait)
CLKOUT
DADR
XCS0, DCS0 to 5
DRD
DB
(b)
(c)
(a)
(d)
(e)
(f)
(g) (h)
(8)
CXD2931R
(2) Write (byte access/no data wait)
CLKOUT
(b)
DADR
(c)
XCS0, DCS0 to 5
DWR
DB
No.
Item
(a) Read/write cycle time (Fex: @20MHz)
(b) Address delay time
(c) Chip select fall delay time
(d) Chip select rise delay time
(e) Read signal fall delay time
(f) Read signal rise delay time
(g) Read data setup time
(h) Read data hold time
(i) Write signal fall delay time
(j) Write signal rise delay time
(k) Write data established time
(l) Write data hold time
(a)
(d)
(i)
(j)
(k)
(l)
(8)
Min.
—
—
4
4
2
3
16
0
0
0
—
5
– 18 –
Typ.
Max.
Unit
100
—
ns
—
9
ns
—
13
ns
—
13
ns
—
8
ns
—
10
ns
—
—
ns
—
—
ns
—
1
ns
—
2
ns
—
7
ns
—
—
ns
∗ The load capacitance = 30pF.