28F016SV Просмотр технического описания (PDF) - Intel
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28F016SV Datasheet PDF : 63 Pages
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28F016SV FlashFile™ MEMORY
2.1 Lead Descriptions
Symbol
Type
Name and Function
A0
INPUT
BYTE-SELECT ADDRESS: Selects between high and low byte when
device is in x8 mode. This address is latched in x8 data programs. Not
used in x16 mode (i.e., the A0 input buffer is turned off when BYTE# is
high).
A1–A15
INPUT
WORD-SELECT ADDRESSES: Select a word within one 64-Kbyte block.
A6–15 selects 1 of 1024 rows, and A1–5 selects 16 of 512 columns. These
addresses are latched during data programs.
A16–A20
INPUT
BLOCK-SELECT ADDRESSES: Select 1 of 32 Erase blocks. These
addresses are latched during data programs, erase and lock block
operations.
DQ0–DQ7
INPUT/OUTPUT
LOW-BYTE DATA BUS: Inputs data and commands during CUI program
cycles. Outputs array, buffer, identifier or status data in the appropriate
read mode. Floated when the chip is de-selected or the outputs are
disabled.
DQ8–DQ15
INPUT/OUTPUT
HIGH-BYTE DATA BUS: Inputs data during x16 data program
operations. Outputs array, buffer or identifier data in the appropriate read
mode; not used for Status Register reads. Floated when the chip is de-
selected or the outputs are disabled.
CE0#, CE1#
RP#
INPUT
INPUT
CHIP ENABLE INPUTS: Activate the device’s control logic, input buffers,
decoders and sense amplifiers. With either CE0# or CE1# high, the device
is de-selected and power consumption reduces to standby levels upon
completion of any current data program or erase operations. Both CE0#
and CE1# must be low to select the device.
All timing specifications are the same for both signals. Device Selection
occurs with the latter falling edge of CE0# or CE1#. The first rising edge of
CE0# or CE1# disables the device.
RESET/POWER-DOWN: RP# low places the device in a deep power-
down state. All circuits that consume static power, even those circuits
enabled in standby mode, are turned off. When returning from deep
power-down, a recovery time of tPHQV is required to allow these circuits to
power-up.
When RP# goes low, any current or pending WSM operation(s) are
terminated, and the device is reset. All Status Registers return to ready
(with all status flags cleared).
Exit from deep power-down places the device in read array mode.
OE#
INPUT
OUTPUT ENABLE: Gates device data through the output buffers when
low. The outputs float to tri-state off when OE# is high.
NOTE:
CEx# overrides OE#, and OE# overrides WE#.
WE#
INPUT
WRITE ENABLE: Controls access to the CUI, Page Buffers, Data Queue
Registers and Address Queue Latches. WE# is active low, and latches
both address and data (command or array) on its rising edge.
Page Buffer addresses are latched on the falling edge of WE#.
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