ATSAMA5D31A-CFU Просмотр технического описания (PDF) - Atmel Corporation

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ATSAMA5D31A-CFU

SMART ARM-based MPU

Atmel Corporation 

9. ARM Cortex-A5

9.1 Description

The ARM Cortex-A5 processor is a high-performance, low-power, ARM macrocell with an L1 cache subsystem

that provides full virtual memory capabilities. The Cortex-A5 processor implements the ARMv7 architecture and

runs 32-bit ARM instructions, 16-bit and 32-bit Thumb instructions, and 8-bit Java™ byte codes in Jazelle® state.

The Floating-Point Unit (FPU) supports the ARMv7 VFPv4-D16 architecture without Advanced SIMD extensions

(NEON). It is tightly integrated to the Cortex-A5 processor pipeline. It provides trapless execution and is optimized

for scalar operation. It can generate an Undefined instruction exception on vector instructions that enables the

programmer to emulate vector capability in software. See the Cortex-A5 Floating-Point Unit Technical Reference

Manual.

Note: All ARM publications referenced in this datasheet can be found at www.arm.com.

9.1.1

Power Management

The Cortex-A5 design supports the following main levels of power management:

 Run Mode

 Standby Mode

9.1.1.1 Run Mode

Run mode is the normal mode of operation where all of the processor functionality is available. Everything,

including core logic and embedded RAM arrays, is clocked and powered up.

9.1.1.2 Standby Mode

Standby mode disables most of the clocks of the processor, while keeping it powered up. This reduces the power

drawn to the static leakage current, plus a small clock power overhead required to enable the processor to wake

up from Standby mode. The transition from Standby mode to Run mode is caused by one of the following:

 the arrival of an interrupt, either masked or unmasked

 the arrival of an event, if standby mode was initiated by a Wait for Event (WFE) instruction

 a debug request, when either debug is enabled or disabled

 a reset.

9.2 Embedded Characteristics

 In-order pipeline with dynamic branch prediction

 ARM, Thumb, and ThumbEE instruction set support

 Harvard level 1 memory system with a Memory Management Unit (MMU)

 32 Kbytes Data Cache

 32 Kbytes Instruction Cache

 64-bit AXI master interface

 ARM v7 debug architecture

 VFPv4-D16 FPU with trapless execution

 Jazelle hardware acceleration

40 SAMA5D3 Series [DATASHEET]

Atmel-11121F-ATARM-SAMA5D3-Series-Datasheet_02-Feb-16

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