ATSAMA5D31A-CFU Просмотр технического описания (PDF) - Atmel Corporation

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ATSAMA5D31A-CFU

SMART ARM-based MPU

Atmel Corporation 

5.1 Embedded Memories

5.1.1

Internal SRAM

The SAMA5D3 embeds a total of 128 Kbytes high-speed SRAM0 and SRAM1. After Remap the SRAM is

accessible at address 0 but also at address 0x00300000. Only the ARM core has access to the SRAM at address

0. The others masters (DMA, peripherals, etc.) always access the SRAM at address 0x00300000.

SRAM0 and SRAM1 can be accessed in parallel to improve the overall bandwidth of the system.

5.1.2

Internal ROM

The SAMA5D3 embeds one 160-Kbyte internal ROM containing a standard and a secure bootloader. The secure

bootloader is described in a separate document, under NDA. The standard bootloader supports booting from:

 8-bit NAND Flash with ECC management

 SPI Serial Flash

 SDCARD

 EMMC

 TWI EEPROM

The boot sequence can be selected using the boot order facility (Boot Sequence Controller Configuration

Register). The internal ROM embeds Galois field tables that are used to compute NAND Flash ECC. Refer to

Figure 11-9 “Galois Field Table Mapping” in Section 11. “Standard Boot Strategies”.

5.1.3

Boot Strategies

For standard boot strategies, refer to Section 11. “Standard Boot Strategies”.

For secure boot strategies, refer to the application note “SAMA5D3x Secure Boot Strategy” (NDA required).

5.2 External Memory

The SAMA5D3 features interfaces to offer connexion to a wide range of external memories or to parallel

peripherals.

5.2.1

DDR2/LPDDR/LPDDR2 Interface

 32-bit external interface

 512 Mbytes address space on CS1

 Supports DDR2, LPDDR and LPDDR2 memories

 Drive level control

 I/O impedance control embedded

 Supports 4-banks and 8-banks and up to 512 Mbytes

 Multi-port

5.2.2

Static Memories and NAND Flash

The static memory controller is dedicated to interfacing external memory devices:

The static memory controller is able to drive up to four chip selects. NCS3 is dedicated to the NAND Flash control.

 Asynchronous SRAM-like memories and parallel peripherals

 NAND Flash (8-bit MLC and SLC)

The SMC embeds a NAND Flash Controller (NFC). The NFC can handle automatic transfers, sending the

commands and address cycles to the NAND Flash and transferring the contents of the page (for read and write) to

the NFC SRAM. It minimizes the CPU overhead.

SAMA5D3 Series [DATASHEET]

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Atmel-11121F-ATARM-SAMA5D3-Series-Datasheet_02-Feb-16

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