MAX19700 Просмотр технического описания (PDF) - Maxim Integrated

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MAX19700

7.5Msps, Ultra-Low-Power Analog Front-End

Maxim Integrated 

7.5Msps, Ultra-Low-Power

Analog Front-End

SPI Timing

The serial digital interface is a standard 3-wire connec-

tion compatible with SPI/QSPI™/MICROWIRE/DSP inter-

faces. Set CS low to enable the serial data loading at

DIN. Following a CS high-to-low transition, data is shift-

ed synchronously, most significant bit first, on the rising

edge of the serial clock (SCLK). After 16 bits are loaded

into the serial input register, data is transferred to the

latch when CS transitions high. CS must transition high

for a minimum of 80ns before the next write sequence.

The SCLK can idle either high or low between transi-

tions. Figure 6 shows the detailed timing diagram of the

3-wire serial interface.

QSPI is a trademark of Motorola, Inc.

Mode-Recovery Timing

Figure 7 shows the mode-recovery timing diagram.

tWAKE is the wakeup time when exiting shutdown, idle,

or standby mode and entering Rx or Tx mode. tENABLE

is the recovery time when switching between either Rx

or Tx mode. tWAKE or tENABLE is the time for the Rx ADC

to settle within 1dB of specified SINAD performance and

Tx DAC settling to 10 LSB error. tWAKE and tENABLE

times are measured after either the 16-bit serial com-

mand is latched into the MAX19700 by a CS transition

high (SPI controlled) or a T/R logic transition (external

Tx-Rx control). In FAST mode, the recovery time is 1µs

to switch between Tx or Rx modes.

Table 3. MAX19700 Mode Control

REGISTER D11

NAME

(MSB)

D10

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A3 A2 A1 A0

15

14 13 12 11 10 9

8

7

6

5

4

3

2

1

ENABLE-16

E11 = 0

Reserved

E10 = 0

Reserved

—

— E7 E6 E5 E4 E3 E2 E1 E0

0

0

0

0

Aux-DAC1

Aux-DAC2

1D11

2D11

1D10 1D9 1D8 1D7 1D6 1D5 1D4 1D3 1D2 1D1 1D0 0 0 0 1

2D10 2D9 2D8 2D7 2D6 2D5 2D4 2D3 2D2 2D1 2D0 0 0 1 0

Aux-DAC3

IOFFSET

3D11

—

3D10 3D9 3D8 3D7 3D6 3D5 3D4 3D3 3D2 3D1 3D0 0 0 1 1

—

— — — — IO5 IO4 IO3 IO2 IO1 IO0 0 1 0 0

QOFFSET

—

COMSEL

—

—

— — — — QO5 QO4 QO3 QO2 QO1 QO0 0 1 0 1

—

— — — — — — — — CM1 CM0 0 1 1 0

Table 4. Power-Management Modes

ADDRESS

DATA BITS

T/R

A3 A2 A1 A0 E3 E2 E1 E0 PIN 27

MODE

X000

X

SHDN

0000

X001

X

IDLE

X = Don't care.

X010

X

STBY

FUNCTION

(POWER

MANAGEMENT)

SHUTDOWN

IDLE

STANDBY

DESCRIPTION

Rx ADC = OFF

Tx DAC = OFF

Aux-DAC = OFF

REF = OFF

Rx ADC = OFF

Tx DAC = OFF

Aux-DAC = Last State

CLK = ON

REF = ON

Rx ADC = OFF

Tx DAC = OFF

Aux-DAC = Last State

CLK = OFF

REF = ON

COMMENT

Device is in complete

shutdown

Overrides T/R pin

Fast turn-on time

Moderate idle power

Overrides T/R pin

Slow turn-on time

Low standby power

Overrides T/R pin

20 ______________________________________________________________________________________

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