MAX19700 Просмотр технического описания (PDF) - Maxim Integrated

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MAX19700

7.5Msps, Ultra-Low-Power Analog Front-End

Maxim Integrated 

7.5Msps, Ultra-Low-Power

Analog Front-End

INTERNAL

BIAS

S2a

S4a

IAP

C2a

S4c

S1

COM

S5a

C1a

S3a

OUT

IAN

S4b

C2b

OUT

C1b

S3b

S2b

INTERNAL

BIAS

INTERNAL

BIAS

S5b

COM

COM

HOLD

HOLD

CLK

TRACK

INTERNAL

TRACK NONOVERLAPPING

CLOCK SIGNALS

S2a

S5a

C1a

S3a

S4a

QAP

C2a

S4c

S1

OUT

MAX19700

QAN

S4b

C2b

OUT

C1b

S2b

INTERNAL

BIAS

S3b

S5b

COM

Figure 1. MAX19700 Rx ADC Internal T/H Circuits

To operate the device in TDD applications, configure

the MAX19700 for Tx or Rx mode with the 3-wire serial

interface. The Rx ADC and Tx DAC share a common

digital bus to reduce the digital I/O to a single 10-bit

parallel multiplexed bus.

Dual 10-Bit Rx ADC

The ADC uses a seven-stage, fully differential, pipelined

architecture that allows for high-speed conversion while

minimizing power consumption. Samples taken at the

inputs move progressively through the pipeline stages

every half clock cycle. Including the delay through the

output latch, the total clock-cycle latency is 5 clock

cycles for channel IA and 5.5 clock cycles for channel

QA. The ADC full-scale analog input range is ±VREF

with a VDD / 2 ±0.2V common-mode input range. VREF

is the difference between VREFP and VREFN. See the

Reference Configurations section for details.

Input Track-and-Hold (T/H) Circuits

Figure 1 displays a simplified diagram of the Rx ADC

input track-and-hold (T/H) circuitry. Both ADC inputs

(IAP, QAP, IAN, and QAN) can be driven either differ-

entially or single-ended. Match the impedance of IAP

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