MAX19700 Просмотр технического описания (PDF) - Maxim Integrated

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MAX19700

7.5Msps, Ultra-Low-Power Analog Front-End

Maxim Integrated 

7.5Msps, Ultra-Low-Power

Analog Front-End

Table 1. Output Codes vs. Input Voltage

DIFFERENTIAL INPUT

VOLTAGE

VREF x 512/512

VREF x 511/512

VREF x 1/512

VREF x 0/512

-VREF x 1/512

-VREF x 511/512

-VREF x 512/512

DIFFERENTIAL INPUT (LSB)

511 (+Full Scale – 1 LSB)

510 (+Full Scale – 2 LSB)

+1

0 (Bipolar Zero)

-1

-511 (-Full Scale +1 LSB)

-512 (-Full Scale)

OFFSET BINARY (D0–D9)

11 1111 1111

11 1111 1110

10 0000 0001

10 0000 0000

01 1111 1111

00 0000 0001

00 0000 0000

OUTPUT DECIMAL CODE

1023

1022

513

512

511

1

0

and IAN, as well as QAP and QAN, and set the input

signal common-mode voltage within the ADC range of

VDD/ 2 (±200mV) for optimum performance.

ADC System Timing Requirements

Figure 3 shows the relationship between the clock, ana-

log inputs, DR indicator, and the resulting output data.

Channel I (CHI) and channel Q (CHQ) are sampled on

the rising edge of the clock signal (CLK) and the result-

ing data is multiplexed at the D0–D9 outputs. CHI data

is updated on the rising edge and CHQ data is updat-

ed on the falling edge of the CLK. The DR indicator fol-

lows CLK with a typical delay time of 8.5ns and remains

high when CHI data is updated and low when CHQ

data is updated. Including the delay through the output

11 1111 1111

11 1111 1110

11 1111 1101

1 LSB = 2 x VREF

1024

VREF

VREF = VREFP - VREFN

VREF

10 0000 0001

10 0000 0000

01 1111 1111

(COM)

00 0000 0011

00 0000 0010

00 0000 0001

00 0000 0000

-512 -511 -510 -509

-1 0+ 1

(COM)

INPUT VOLTAGE (LSB)

+509 +510 +511 +512

Figure 2. ADC Transfer Function

latch, the total clock-cycle latency is 5 clock cycles for

CHI and 5.5 clock cycles for CHQ.

Digital Input/Output Data (D0–D9)

D0–D9 are the Rx ADC digital logic outputs when the

MAX19700 is in receive mode. This bus is shared with

the Tx DAC digital logic inputs and operates in half-

duplex mode. D0–D9 are the Tx DAC digital logic

inputs when the MAX19700 is in transmit mode. The

logic level is set by OVDD from 1.8V to VDD. The digital

output coding is offset binary (Table 1). Keep the

capacitive load on the digital outputs D0–D9 as low as

possible (<15pF) to avoid large digital currents feeding

back into the analog portion of the MAX19700 and

degrading its dynamic performance. Buffers on the dig-

ital outputs isolate the outputs from heavy capacitive

loads. Adding 100Ω resistors in series with the digital

outputs close to the MAX19700 will help improve ADC

performance. See the MAX19700EVKIT schematic for

an example of the digital outputs driving a digital buffer

through 100Ω series resistors.

During SHDN, IDLE, and STBY states, the pins D0–D9

are internally pulled up to prevent floating digital inputs.

To ensure no current flows through D0–D9 I/O, the

external bus needs to be either tri-stated or pulled up to

OVDD and should not be pulled to ground.

Dual 10-Bit Tx DAC and Transmit Path

The dual 10-bit digital-to-analog converters (Tx DAC)

operate with clock speeds up to 7.5MHz. The Tx DAC

digital inputs, D0–D9, are multiplexed on a single 10-bit

bus. The voltage reference determines the Tx path full-

scale output voltage. See the Reference Configurations

section for details on setting the reference voltage. Each

Tx path channel integrates a lowpass filter tuned to

meet the TD-SCDMA spectral mask requirements. The

TD-SCDMA filters are tuned for 1.27MHz cutoff frequen-

cy and >55dB image rejection at fIMAGE = 4.32MHz,

fOUT = 800kHz, and fCLK = 5.12MHz. See Figure 4 for

an illustration of the filter frequency response.

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