MAX17040(2010) Просмотр технического описания (PDF) - Maxim Integrated
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MAX17040 Datasheet PDF : 13 Pages
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Compact, Low-Cost 1S/2S Fuel Gauges
ELECTRICAL CHARACTERISTICS: 2-WIRE INTERFACE
(2.5V ≤ VDD ≤ 4.5V, TA = -20°C to +70°C.)
PARAMETER
SCL Clock Frequency
Bus Free Time Between a STOP
and START Condition
SYMBOL
fSCL (Note 5)
tBUF
CONDITIONS
MIN TYP MAX UNITS
0
400
kHz
1.3
µs
Hold Time (Repeated)
START Condition
tHD:STA (Note 5)
0.6
µs
Low Period of SCL Clock
High Period of SCL Clock
Setup Time for a Repeated
START Condition
tLOW
tHIGH
tSU:STA
1.3
µs
0.6
µs
0.6
µs
Data Hold Time
Data Setup Time
Rise Time of Both SDA
and SCL Signals
tHD:DAT
tSU:DAT
(Notes 6, 7)
(Note 6)
tR
0
100
20 +
0.1CB
0.9
µs
ns
300
ns
Fall Time of Both SDA
and SCL Signals
Setup Time for STOP Condition
Spike Pulse Widths Suppressed
by Input Filter
tF
tSU:STO
tSP
(Note 8)
20 +
0.1CB
0.6
0
300
ns
µs
50
ns
Capacitive Load for Each
Bus Line
CB
(Note 9)
400
pF
SCL, SDA Input Capacitance
CBIN
60
pF
Note 1: All voltages are referenced to VSS.
Note 2: SDA, SCL = VSS; EO, SEO idle.
Note 3: External time base on EO pin must meet this specification.
Note 4: The MAX17040/MAX17041 enter Sleep mode 1.75s to 2.5s after (SCL < VIL) AND (SDA < VIL).
Note 5: fSCL must meet the minimum clock low time plus the rise/fall times.
Note 6: The maximum tHD:DAT has only to be met if the device does not stretch the low period (tLOW) of the SCL signal.
Note 7: This device internally provides a hold time of at least 75ns for the SDA signal (referred to the VIHMIN of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
Note 8: Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instant.
Note 9: CB—total capacitance of one bus line in pF.
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