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MAX17040(2010) Просмотр технического описания (PDF) - Maxim Integrated

Номер в каталоге
Компоненты Описание
производитель
MAX17040
(Rev.:2010)
MaximIC
Maxim Integrated MaximIC
MAX17040 Datasheet PDF : 13 Pages
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Table 1. Register Summary
ADDRESS
(HEX)
REGISTER
DESCRIPTION
02h–03h
VCELL
Reports 12-bit A/D measurement of battery voltage.
04h–05h
06h–07h
08h–09h
SOC
MODE
VERSION
Reports 16-bit SOC result calculated by ModelGauge algorithm.
Sends special commands to the IC.
Returns IC version.
0Ch–0Dh
RCOMP
Battery compensation. Adjusts IC performance based on
application conditions.
FEh–FFh
COMMAND Sends special commands to the IC.
READ/
WRITE
R
R
W
R
R/W
W
DEFAULT
(HEX)
9700h
VCELL Register
Battery voltage is measured at the CELL pin input with
respect to GND over a 0 to 5.00V range for the
MAX17040 and 0 to 10.00V for the MAX17041 with res-
olutions of 1.25mV and 2.50mV, respectively. The A/D
calculates the average cell voltage for a period of
125ms after IC POR and then for a period of 500ms for
every cycle afterwards. The result is placed in the
VCELL register at the end of each conversion period.
Figure 3 shows the VCELL register format.
SOC Register
The SOC register is a read-only register that displays
the state of charge of the cell as calculated by the
ModelGauge algorithm. The result is displayed as a
percentage of the cell’s full capacity. This register
automatically adapts to variation in battery size since
the MAX17040/MAX17041 naturally recognize relative
SOC. Units of % can be directly determined by observ-
ing only the high byte of the SOC register. The low byte
provides additional resolution in units 1/256%. The
reported SOC also includes residual capacity, which
might not be available to the actual application because
of early termination voltage requirements. When SOC()
= 0, typical applications have no remaining capacity.
The first update occurs 125ms after POR of the IC.
Subsequent updates occur at variable intervals
depending on application conditions. ModelGauge cal-
culations outside the register are clamped at minimum
and maximum register limits. Figure 4 shows the SOC
register format.
MSB—ADDRESS 02h
211 210 29
28
27
26
25
24
MSB
LSB
0: BITS ALWAYS READ LOGIC 0
Figure 3. VCELL Register Format
LSB—ADDRESS 03h
23
22
21
20
0
0
0
0
MSB
LSB
UNITS: 1.25mV FOR MAX17040
2.50mV FOR MAX17041
27
26
MSB
MSB—ADDRESS 04h
25
24
23
22
21
20
LSB
Figure 4. SOC Register Format
2-1 2-2
MSB
LSB—ADDRESS 05h
2-3 2-4 2-5 2-6
2-7 2-8
LSB
UNITS: 1.0%
_______________________________________________________________________________________ 7

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