CY7C056V-20AI Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C056V-20AI Datasheet PDF : 22 Pages
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PRELIMINARY
CY7C056V
CY7C057V
Bus Match Operation
The right port of the CY7C057V 32Kx36 dual-port SRAM can
be configured in a 36-bit long-word, 18-bit word, or 9-bit byte
format for data I/O. The data lines are divided into four lanes,
each consisting of 9 bits (byte-size data lines).
BA WA
9
CY7C056V
/
CY7C057V
9
x36 16K/32Kx36
/
9
/
Dual Port
/
9
/
x9, x18, x36
/
BM SIZE
The Bus Match Select (BM) pin works with Bus Size Select
(SIZE) to select bus width (long-word, word, or byte) for the
right port of the dual-port device. The data sequencing ar-
rangement is selected using the Word Address (WA) and Byte
Address (BA) input pins. A logic “0” applied to both the Bus
Match Select (BM) pin and to the Bus Size Select (SIZE) pin
will select long-word (36-bit) operation. A logic “1” level applied
to the Bus Match Select (BM) pin will enable either byte or
word bus width operation on the right port I/Os depending on
the logic level applied to the SIZE pin. The level of Bus Match
Select (BM) must be static throughout device operation.
Normally, the Bus Size Select (SIZE) pin would have no stan-
dard-cycle application when BM = LOW and the device is in
long-word (36-bit) operation. A “special” mode has been add-
ed however to disable ALL right port I/Os while the chip is
active. This I/O disable mode is implemented when SIZE is
forced to a logic “1” while BM is at a logic “0”. It allows the bus-
matched port to support a chip enable “Don’t Care” sema-
phore read/write access similar to that provided on the left port
of the device when all Byte Select (B0–3) control inputs are
deselected.
The Bus Size Select (SIZE) pin selects either a byte or word
data arrangement on the right port when the Bus Match Select
(BM) pin is HIGH. A logic “1” on the SIZE pin when the BM pin
is HIGH selects a byte bus (9-bit) data arrangement). A logic
“0” on the SIZE pin when the BM pin is HIGH selects a word
bus (18-bit) data arrangement. The level of the Bus Size Select
(SIZE) must also be static throughout normal device operation.
Long-Word (36-bit) Operation
Bus Match Select (BM) and Bus Size Select (SIZE) set to a
logic “0” will enable standard cycle long-word (36-bit) opera-
tion. In this mode, the right port’s I/O operates essentially in an
identical fashion as does the left port of the dual-port SRAM.
However no Byte Select control is available. All 36 bits of the
long-word are shifted into and out of the right port’s I/O buffer
stages. All read and write timing parameters may be identical
with respect to the two data ports. When the right port is con-
figured for a long-word size, Word Address (WA), and Byte
Address (BA) pins have no application and their inputs are
“Don’t Care”[51] for the external user.
Word (18-bit) Operation
Word (18-bit) bus sizing operation is enabled when Bus Match
Select (BM) is set to a logic “1” and the Bus SIze Select (SIZE)
pin is set to a logic “0”. In this mode, 18 bits of data are ported
through I/O0R–17R. The level applied to the Word Address
(WA) pin during word bus size operation determines whether
the most-significant or least-significant data bits are ported
through the I/O0R–17R pins in an Upper Word/Lower Word se-
lect fashion (note that when the right port is configured for word
size operation, the Byte Address pin has no application and its
input is “Don’t Care”[51]).
Device operation is accomplished by treating the WA pin as an
additional address input and using standard cycle address and
data setup/hold times. When transferring data in word (18-bit)
bus match format, the unused I/O18R–35R pins are three-stated.
Byte (9-bit) Operation
Byte (9-bit) bus sizing operation is enabled when Bus Match
Select (BM) is set to a logic “1” and the Bus Size Select (SIZE)
pin is set to a logic “1”. In this mode, data is ported through
I/O0R–8R in four groups of 9-bit bytes. A particular 9-bit byte
group is selected according to the levels applied to the Word
Address (WA) and Byte Address (BA) input pins.
I/Os
Rank
WA
BA
I/O27R–35R
Upper-MSB
1
1
I/O18R–26R
Lower-MSB
1
0
I/O9R–17R
Upper-MSB
0
1
I/O0R–8R
Lower-MSB
0
0
Device operation is accomplished by treating the Word Ad-
dress (WA) pin and the Byte Address (BA) pins as additional
address inputs having standard cycle address and data set-
up/hold times. When transferring data in byte (9-bit) bus match
format, the unused I/O9R–35R pins are three-stated.
Note:
51. Even though a logic level applied to a “Don’t Care” input will not change the logical operation of the dual-port, inputs that are temporarily a “Don’t Care” (along
with unused inputs) must not be allowed to float. They must be forced either HIGH or LOW.
19
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