UPD75P3216 Просмотр технического описания (PDF) - NEC => Renesas Technology
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UPD75P3216 Datasheet PDF : 56 Pages
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µPD75P3216
4. Mk I AND Mk II MODE SELECTION FUNCTION
Setting a stack bank selection (SBS) register for the µPD75P3216 enables the program memory to be switched
between Mk I mode and Mk II mode. This function is applicable when using the µPD75P3216 to evaluate the µPD753204,
753206, or 753208.
When the SBS bit 3 is set to 1: sets Mk I mode (supports Mk I mode for µPD753204, 753206, and 753208)
When the SBS bit 3 is set to 0: sets Mk II mode (supports Mk II mode for µPD753204, 753206, and 753208)
4.1 Difference between Mk I Mode and Mk II Mode
Table 4-1 lists points of difference between the Mk I mode and the Mk II mode for the µPD75P3216.
Table 4-1. Difference between Mk I Mode and Mk II Mode
Item
Mk I Mode
Program counter
PC13-0
Program memory (bytes)
16384
Data memory (bits)
512 × 4
Stack
Stack bank
Selectable via memory banks 0, 1
No. of stack bytes
2 bytes
Instruction BRA !addr1 instruction None
CALLA !addr1 instruction
Instruction CALL !addr instruction
execution time CALLF !faddr instruction
3 machine cycles
2 machine cycles
Supported mask ROMs
When set to Mk I mode:
µPD753204, 753206, and 753208
Mk II Mode
3 bytes
Provided
4 machine cycles
3 machine cycles
When set to Mk II mode:
µPD753204, 753206, and 753208
Caution The Mk II mode supports a program area which exceeds 16K bytes in the 75X and 75XL series. This
mode enhances the software compatibility with products which have more than 16K bytes.
When the Mk II mode is selected, the number of stack bytes used in execution of a subroutine call
instruction increases by 1 per stack for the usable area compared to the Mk I mode. Furthermore,
when a CALL !addr, or CALLF !faddr instruction is used, each instruction takes another machine
cycle. Therefore, when more importance is attached to RAM utilization or throughput than software
compatibility, use the Mk I mode.
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