TC35274 Просмотр технического описания (PDF) - Toshiba

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TC35274

TOSHIBA MPEG-4 Video Decoder LSI

Toshiba 

Preliminary

MPEG-4 Video Decoder LSI

TC35274

3. Interface Specifications

3.1 Host Interface

An external host CPU can access to TC35274 via a host interface. The access timing of a read,

a write, and an interrupt operation are explained below. The host interface has two access modes;

handshake access mode and synchronized access mode.

3.1.1 Handshake access mode

In this mode, the host CPU has to finish an access operation after a waiting signal (/HWAIT)

becomes high.

Fig.3 shows the timing diagram of a read operation. A read access starts by asserting both a chip

select signal (/HCS) and a read signal (/RD) (timing (a)). At this timing, /HWAIT becomes low. When

the read data are ready, /HWAIT becomes high (timing (b)). The host CPU gets the read data and

finishes the read operation by negating both /HCS and /HRD (timing (c)).

Fig.4 shows the timing diagram of a write operation. A write access starts by asserting both /HCS

and a write signal (/WR) (timing (a)). At this timing, /HWAIT becomes low. When TC35274 gets the

write data, /HWAIT becomes high (timing (b)). After that, the host CPU finishes the write operation by

negating both /HCS and /HWR (timing (c)).

/HCS

HADDR

/HRD

/HWAIT

HDAT

(a)

TCSS

TADS

(b)

(c)

TCSH

TADH

TRR

TWTAD

TWTID

TDTVD

TRDH

TDTRS

TDTID

TDTOD

Fig. 3 Read Operation in handshake mode

TOSHIBA Confidential

7/13

Version 0.90

2000-4-27

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