TC35274 Просмотр технического описания (PDF) - Toshiba

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TC35274

TOSHIBA MPEG-4 Video Decoder LSI

Toshiba 

Preliminary

MPEG-4 Video Decoder LSI

TC35274

Table 8 Display Interface Timing

Parameter

Description

Min

TCYCLE

Cycle time of DISPCLK

100

TSETUP

Setup time of DISPHSYN and DISPVSYN

2

THOLD

Hold time DISPHSYN and DISPVSYN

2

TDELAY

Delay time of DISPBLK and DISPPXL

* When system clock is 40MHz, DSPCLK has to be less than 10MHz.

Max

(TSYSCLK*3)+15

Unit

ns

ns

ns

ns

4. Electric Specifications

4.1 TBD.

TOSHIBA Confidential

13/13

Version 0.90

2000-4-27

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