TC35274 Просмотр технического описания (PDF) - Toshiba
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TC35274 Datasheet PDF : 13 Pages
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Preliminary
MPEG-4 Video Decoder LSI
TC35274
Table 7 Host Interface Timing
Parameters
Description
TCSS
TCSH
TADS
TADH
TWTAD
TWTID
TACS
TACID
TDTOD
TDTVD
TDTRS
TDTwS
tDTID
TRDH
TRR
Setup time of HCS.
Hold time of HCS.
Setup time of Address.
Hold time of Address.
Delay time of /HWAIT for /HRD or /HWR.
Access time in handshake access mode.*
Access time in synchronized access mode.
Delay time of HACK
Delay time of Data.
Data hold time.
Read data setup time.
Write data setup time.
Data hold time.
Hold time of /HRD.
Recovery time of /HRD or /HWR
* TSYSCLK means the cycle time of TC35274 internal system clock.
Min
0.0
0.0
0.0
0.0
*3 TSYSCLK
*3 TSYSCLK
*2 TSYSCLK
*1 TSYSCLK
0.0
0.0
*3 TSYSCLK
Max
15.0
TSYSCLK*100
15.0
15.0
*99 TSYSCLK
15.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
* Access to internal DRAM requires Tsysclk*100 (ns) in a worst case. As for the others accesses, it
takes 3 cycles of the internal system clock.
TOSHIBA Confidential
11/13
Version 0.90
2000-4-27
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