M69AR024BL70ZB8T(2003) Просмотр технического описания (PDF) - STMicroelectronics
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M69AR024BL70ZB8T Datasheet PDF : 32 Pages
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M69AR024B
Table 8. Write Mode AC Characteristics
M69AR024B
Symbol Alt.
Parameter
-70, -80
Unit
Min
Max
tAVAX (1,2) tWC Write Cycle Time
80
1000
ns
tAVBL (2)
tAS Address Valid to LB, UB Low
0
ns
tAVEL (2)
tAS Address Valid to Chip Enable Low
0
ns
tAVWL (2) tAS Address Valid to Write Enable Low
0
ns
tAXAV (5) tAXW Address Invalid Time for Write
10
ns
tBHAX (4) tBR LB, UB High to Address Transition
15
1000
ns
tBHDX
tDH LB, UB High to Input Transition
0
ns
tBLBH (3) tBW LB, UB Low to LB, UB High
75
ns
tBLBH2 tBWO LB, UB Low to LB, UB High, Pulse Overlap
20
ns
tBLWH (3) tBW LB, UB Low to Write Enable High
75
ns
tDVBH
tDS Input Valid to LB, UB High
30
ns
tDVEH
tDS Input Valid to Chip Enable High
30
ns
tDVWH
tDS Input Valid to Write Enable High
30
ns
tEHAX (4) tWRC Chip Enable High to Address Transition
15
ns
tEHDX
tDH Chip Enable High to Input Transition
0
ns
tEHEL
tCP Chip Enable High to Chip Enable Low
15
ns
tELAX (1,2) tWC Write Cycle Time
80
1000
ns
tELEH (3) tCW Chip Enable Low to Chip Enable High
75
ns
tGHAV (7) tOES Output Enable High to Address Valid
0
ns
tGHEL (6) tOHCL Output Enable High to Chip Enable Low
–5
ns
tWHAX (4) tWR Write Enable High to Address Transition
15
1000
ns
tWHDX
tDH Write Enable High to Input Transition
0
ns
tWLBH (3) tWP Write Enable Low to LB, UB High
65
ns
tWLWH (3) tWP Write Enable Low to Write Enable High
65
1000
ns
Note: 1. Maximum value is applicable if E1 is kept at Low without any address change. If needed by system operation, please contact your
local ST representative for relaxation of the 1000ns limitation.
2. Minimum value must be equal to or greater than the sum of write pulse (tELEH, tWLWH or tBLBH) and write recovery time (tWRC,
tWR or tBR).
3. Write pulse is defined from the falling edge of E1, W, or LB/UB, whichever occurs last.
4. Write recovery is defined from Write pulse is defined from the rising edge of E1, W, or LB/UB, whichever occurs first.
5. Applicable to any address change when E1 stays Low.
6. If G is Low after minimum tGHEL, the read cycle is initiated. In other words, G must be brought High within 5ns after E1 is brought
Low. Once the read cycle is initiated, new write pulse should be input after minimum Read Cycle Time is met.
7. If G is Low after new address input, the read cycle is initiated. In other words, G must be brought High at the same time or before
new address valid. Once the read cycle is initiated, new write pulse should be input after minimum Read Cycle Time is met.
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