M69AR024BL70ZB8T(2003) Просмотр технического описания (PDF) - STMicroelectronics
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M69AR024BL70ZB8T Datasheet PDF : 32 Pages
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M69AR024B
Table 7. Read Mode AC Characteristics
M69AR024B
Symbol Alt.
Parameter
-70
-80
Unit
Min Max Min Max
tAVAX (1,2) tRC Address Valid Time
80 1000 80 1000 ns
tAVEL
tASC Address Valid to Chip Enable Low
–5
–5
ns
tAVGL
tASO Address Valid to Output Enable Low
10
10
ns
tAVQV (3,5) tAA Address Valid to Output Valid
70
80
ns
tAXAV (5,8) tAX Address Invalid Time
10
10
ns
tAXQX (3) tOH Data hold from address change
10
10
ns
tBHQX (3) tOH Upper/Lower Byte Enable High to Output Transition 10
10
ns
tBHQZ (4) tBHZ Upper/Lower Byte Enable High to Output Hi-Z
20
20
ns
tBLQV (3) tBA Upper/Lower Byte Enable Low to Output Valid
70
80
ns
tBLQX (4) tBLZ Upper/Lower Byte Enable Low to Output Transition
5
5
ns
tEHAX (9) tCHAH Chip Enable High to Address Invalid
–5
–5
ns
tEHEL
tCP Chip Enable High to Chip Enable Low
15
15
ns
tEHQX (3) tOH Chip Enable High to Output Transition
10
10
ns
tEHQZ (4) tCHZ Chip Enable High to Output Hi-Z
20
20
ns
tELAX (1,2) tRC Read Cycle Time
80 1000 80 1000 ns
tELEH (1,2) tRC Read Cycle Time
80 1000 80 1000 ns
tELQV (3) tCE Chip Enable Low to Output Valid
70
80
ns
tELQX (4) tCLZ Chip Enable Low to Output Transition
10
10
ns
tGHAX tOHAH Output Enable High to Address Invalid
–5
–5
ns
tGHQX (3) tOH Output Data Hold Time
10
10
ns
tGHQZ (4) tOHZ Output Enable High to Output Hi-Z
20
20
ns
tGLQV (3) tOE Output Enable Low to Output Valid
45
45
ns
tGLQX (4) tOLZ Output Enable Low to Output Transition
5
5
ns
Note: 1. Maximum value is applicable if E1 is kept at Low without change of address input of A3 to A19. If needed by system operation,
please contact local ST sales office for the relaxation of 1µs limitation.
2. Address should not be changed within tAVAX(min).
3. The output load 50pF with 50Ω termination to VCC*0.5 V.
4. The output load CL = 5pF without any other load.
5. Applicable to A3 to A19 when E1 is kept at Low.
6. Applicable only to A0, A1 and A2 when E1 is kept at Low for the page address access.
7. In case Page Read Cycle is continued with keeping E1 stays Low, E1 must be brought to High within 4µs. In other words, Page
Read Cycle must be closed within 4µs.
8. Applicable when at least two of address inputs among applicable are switched from previous state.
9. tAVAX(min) must be satisfied.
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