MAX31782(2010) Просмотр технического описания (PDF) - Maxim Integrated

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MAX31782
(Rev.:2010)

System Management Microcontroller

Maxim Integrated 

System Management Microcontroller

Hardware Multiplier

The hardware multiplier (a multiply-accumulate, or MAC

module) is a very powerful tool, especially for applica-

tions that require heavy calculations. This multiplier

can execute the multiply, multiply-negate, or multiply-

accumulate, multiply-subtract operation for signed or

unsigned operands in a single machine cycle, and even

faster for special cases. The MAC module uses eight

SFRs, mapped as register 0h–07h in module M5.

System Interrupts

Multiple interrupt sources are available to respond to

internal and external events. The MAXQ20 architecture

uses a single interrupt vector (IV) and single interrupt-

service routine (ISR) design. For maximum flexibility,

interrupts can be enabled globally, individually, or by

module. When an interrupt condition occurs, its indi-

vidual flag is set, even if the interrupt source is disabled

at the local, module, or global level. Interrupt flags must

be cleared within the firmware-interrupt routine to avoid

repeated interrupts from the same source. Application

software must ensure a delay between the write to the

flag and the RETI instruction to allow time for the inter-

rupt hardware to remove the internal interrupt condition.

Asynchronous interrupt flags require a one-instruction

delay and synchronous interrupt flags require a two-

instruction delay. When an enabled interrupt is detected,

execution jumps to a user-programmable interrupt vec-

tor location. The IV register defaults to 0000h on reset or

power-up, so if it is not changed to a different address,

application firmware must determine whether a jump to

0000h came from a reset or interrupt source.

Once control has been transferred to the ISR, the

Interrupt Identification register (IIR) can be used to deter-

mine if a system register or peripheral register was the

source of the interrupt. In addition to IIR, MIIR registers

are implemented to indicate which particular function

under a peripheral module has caused the interrupt. The

device contains six peripheral modules, M0–M5. An MIIR

register is implemented under each module. The MIIR

registers are 16-bit read-only registers and all of them

default to all 0 on system reset. Once the module that

causes the interrupt is singled out, it can then be inter-

rogated for the specific interrupt source and software

can take appropriate action. Interrupts are evaluated

by application code allowing the definition of a unique

interrupt priority scheme for each application. Interrupt

sources are available from the watchdog timer, the ADC,

the TACH.n pins, the programmable timer/counter, the

I2C-compatible master and slave interface, the SVM, and

the port 6 I/O pins.

Programmable Timer/Counter

The device features a general-purpose programmable

timer/counter commonly referred to as a Timer B mod-

ule. The specification for this timer/counter block is the

same as the Timer B specification. There are four reg-

isters associated with this timer/counter block: TB0CN

(control register), TB0V (value register), TB0C (compare

register), and TB0R (capture/reload value register). The

timer/counter has two pins, TBA and TBB, that are multi-

plexed with pins P6.4 and P6.2, respectively. When TBA

or TBB is enabled, the corresponding pin functions as

a timer/counter pin instead of a GPIO. See the I/O Port

section for more details. Detailed information regarding

the timer/counter block can be found in the MAXQ Family

User’s Guide: MAX31782 Supplement.

I/O Port

The device includes a simple input/output (I/O) data port,

port 6. Pins P6.0–P6.4 are primary GPIO pins with alter-

nate functions. Each pin is multiplexed with at least one

special function, such as interrupts, timer/counter I/O

pins, or JTAG pins. Table 2 summarizes the functionality

of the I/O pins. Figure 4 shows a block diagram of the

I/O port.

Port 6 pins have Schmitt trigger receivers and full CMOS

output drivers, and can support alternate functions. The

port is accessed through six SFRs (PO6, PI6, PD6, EIE6,

EIF6, and EIES6) in module 1 and each pin can be indi-

vidually configured. The pin is either high impedance or

a weak pullup when defined as an input, dependent on

the state of the corresponding bit in the output register.

In addition, each pin can function as external interrupt

with individual enable, flag, and active edge selection,

when programmed as input.

On power-up, pins P6.0–P6.3 default to JTAG. Clearing

SC.TAP to 0 (1 is the power-up state) configures them as

GPIO. Setting EIE6.n (n = 0–4, 6, 7) to 1 configures P6.n

to an interrupt.

Pins P6.2 and P6.4 have special functions that are the

timer/counter’s TBB and TBA pins, respectively. When

TBB or TBA or both are enabled, P6.2 or P6.4 or both

are used as their special functions. P6.2 and P6.4 are

independent when used as timer/counter pins, i.e., when

either of them is used as a timer/counter pin, the other

can still be used as GPIO if the corresponding special

function is not enabled.

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