MAX31782(2010) Просмотр технического описания (PDF) - Maxim Integrated
Номер в каталоге
Компоненты Описание
производитель
MAX31782 Datasheet PDF : 20 Pages
| |||
System Management Microcontroller
Table 1. Power Modes
CKCN.
STOP
0
0
1
1
1
SVM.
SVMEN
0
1
0
1
1
SVM.
SVMSTOP
X
X
X
0
1
CPU
On
On
Off
Off
Off
LDO
(1.8V)
On
On
On
On
On
INTERNAL
OSCILLATOR
On
On
On
On
On
BROWNOUT
DETECT
On
On
On
On
On
SVM
MONITOR
Off
On
Off
Off
On
LDO (1.8V)
MONITOR
On
On
On
On
On
ADC
On/Off
On/Off
Off
Off
Off
POWER
MODE
CPU Mode
CPU Mode
Stop Mode
Stop Mode
Stop Mode
LDO
(2.5V)
On
On
On
On
On
Watchdog Timer Reset
The watchdog timer provides a mechanism to reset the
processor in the case of undesirable code execution.
The watchdog timer is a hardware timer designed to
be periodically reset by the application software. If the
software operates correctly, the timer is reset before it
reaches its maximum count. However, if undesirable
code execution prevents a reset of the watchdog timer,
the timer reaches its maximum count and resets the
processor.
The watchdog timer is controlled through 2 bits in the
WDCN register (WDCN[5:4]: WD[1:0]). Its timeout period
can be set to one of the four programmable intervals
ranging from 212 to 221 system clock (MOSC) periods
(1.024ms to 0.524s). The watchdog interrupt occurs at
the end of this timeout period, which is 512 MOSC clock
periods, or 128µs, before the reset. The reset generated
by the watchdog timer lasts for four system clock cycles,
which is 1µs. Software can determine if a watchdog time
caused a reset by checking the watchdog timer reset
flag (WTRF) in the WDCN register. Execution resumes at
location 8000h following a watchdog timer reset.
External Reset
Asserting the RST pin low causes the device to enter
the reset state. The external reset function is described
in the MAXQ Family User’s Guide. Execution resumes at
location 8000h after the RST pin is released.
Internal System Reset
In I2C bootload mode, the host can issue a BBh com-
mand to reset the communicating device using an I2C
slave address of 34h. This reset has the same effect as
the external reset as far as the reset values of all registers
are concerned. Also, an internal system reset can occur
when the in-system programming is done (ROD = 1).
Power Modes
The device supports two modes of operation: CPU mode
and stop mode. The device enters stop mode state after
a CPU STOP (CKCN.STOP) is asserted. On entering stop
mode, the digital core is inactive as its clock is turned
off. All the analog circuits, except ADC (including SVM,
LDOs, and monitor circuits), are still active. Stop mode
is exited by any of the following: an external interrupt on
port 6, an I2C START interrupt, an SVM interrupt, or an
external reset. For one of the mentioned interrupts to get
the device out of stop mode, it must be enabled. The
system returns to CPU mode within 10 system clocks.
If an interrupt causes the system to come out of stop
mode, the program execution starts from the point where
stop mode was asserted. However, if an external reset is
used to come out of stop mode, the program execution
begins from ORG (starting point). Table 1 explains the
state of analog/digital circuits during different modes.
Register Set
Most functions of the device are controlled by sets of
registers. These registers provide a working space for
memory operations as well as configuring and address-
ing peripheral registers on the device. Registers are
divided into two major types: system registers (SPRs)
and peripheral registers (SFRs). The common register
set, also known as the system registers, includes the
ALU, accumulator registers, data pointers, interrupt vec-
tors and control, and stack pointer. The peripheral regis-
ters define additional functionality and the functionality is
broken up into discrete modules. Both the system regis-
ters and the peripheral registers are illustrated in detail in
the MAXQ Family User’s Guide: MAX31782 Supplement.
13
Share Link: 