HMS30C7202N Просмотр технического описания (PDF) - MagnaChip Semiconductor

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HMS30C7202N

Highly-intergrated MPU

MagnaChip Semiconductor 

HMS30C7202N

12.5.4 UART(Universal Asynchronous Receiver Transmitter)

BAUD CLOCK

DATA OUTPUT

BIT 1

tBAUD

BIT 2

tBIT = 16 BAUD CLOCK

BIT 3

SERIAL OUT(TXD)

THR UPDATE

XMIT EMPTY

THR EMPTY INTR

START

DATA(5-8)

PARITY STOP(1-2)

tBIT

tBAUD+5ns

SERIAL IN(TXD)

XMT FIFO DATA NUM 0

SD

P St

BYTE 1

BYTE 2

BYTE 3

10 1 2 3

2

3 43 4

5

XMT FIFO UPDATE

XMT FIFO EMPTY

BYTE 4

4

BYTE 5

3

SERIAL IN(RXD)

RCV DATA READY

RCV DATA READY INTR

START

DATA(5-8)

PARITY STOP(1-2)

SERIAL IN(RXD)

SD

P St

RCV FIFO DATA NUM0

1

2

3

4

5

6

RCV DATA READY INTR

If FCR[4:3] == 2’h1

© 2004 MagnaChip Semiconductor Ltd. All R1ig71hts Reserved.

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